1*8bab661aSEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8bab661aSEmmanuel Vadot/* 3*8bab661aSEmmanuel Vadot * Device Tree Source for the RZ/Five SoC 4*8bab661aSEmmanuel Vadot * 5*8bab661aSEmmanuel Vadot * Copyright (C) 2022 Renesas Electronics Corp. 6*8bab661aSEmmanuel Vadot */ 7*8bab661aSEmmanuel Vadot 8*8bab661aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 9*8bab661aSEmmanuel Vadot 10*8bab661aSEmmanuel Vadot#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) 11*8bab661aSEmmanuel Vadot 12*8bab661aSEmmanuel Vadot#include <arm64/renesas/r9a07g043.dtsi> 13*8bab661aSEmmanuel Vadot 14*8bab661aSEmmanuel Vadot/ { 15*8bab661aSEmmanuel Vadot cpus { 16*8bab661aSEmmanuel Vadot #address-cells = <1>; 17*8bab661aSEmmanuel Vadot #size-cells = <0>; 18*8bab661aSEmmanuel Vadot timebase-frequency = <12000000>; 19*8bab661aSEmmanuel Vadot 20*8bab661aSEmmanuel Vadot cpu0: cpu@0 { 21*8bab661aSEmmanuel Vadot compatible = "andestech,ax45mp", "riscv"; 22*8bab661aSEmmanuel Vadot device_type = "cpu"; 23*8bab661aSEmmanuel Vadot #cooling-cells = <2>; 24*8bab661aSEmmanuel Vadot reg = <0x0>; 25*8bab661aSEmmanuel Vadot status = "okay"; 26*8bab661aSEmmanuel Vadot riscv,isa = "rv64imafdc"; 27*8bab661aSEmmanuel Vadot mmu-type = "riscv,sv39"; 28*8bab661aSEmmanuel Vadot i-cache-size = <0x8000>; 29*8bab661aSEmmanuel Vadot i-cache-line-size = <0x40>; 30*8bab661aSEmmanuel Vadot d-cache-size = <0x8000>; 31*8bab661aSEmmanuel Vadot d-cache-line-size = <0x40>; 32*8bab661aSEmmanuel Vadot clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 33*8bab661aSEmmanuel Vadot operating-points-v2 = <&cluster0_opp>; 34*8bab661aSEmmanuel Vadot 35*8bab661aSEmmanuel Vadot cpu0_intc: interrupt-controller { 36*8bab661aSEmmanuel Vadot #interrupt-cells = <1>; 37*8bab661aSEmmanuel Vadot compatible = "riscv,cpu-intc"; 38*8bab661aSEmmanuel Vadot interrupt-controller; 39*8bab661aSEmmanuel Vadot }; 40*8bab661aSEmmanuel Vadot }; 41*8bab661aSEmmanuel Vadot }; 42*8bab661aSEmmanuel Vadot}; 43*8bab661aSEmmanuel Vadot 44*8bab661aSEmmanuel Vadot&soc { 45*8bab661aSEmmanuel Vadot interrupt-parent = <&plic>; 46*8bab661aSEmmanuel Vadot 47*8bab661aSEmmanuel Vadot plic: interrupt-controller@12c00000 { 48*8bab661aSEmmanuel Vadot compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; 49*8bab661aSEmmanuel Vadot #interrupt-cells = <2>; 50*8bab661aSEmmanuel Vadot #address-cells = <0>; 51*8bab661aSEmmanuel Vadot riscv,ndev = <511>; 52*8bab661aSEmmanuel Vadot interrupt-controller; 53*8bab661aSEmmanuel Vadot reg = <0x0 0x12c00000 0 0x400000>; 54*8bab661aSEmmanuel Vadot clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; 55*8bab661aSEmmanuel Vadot power-domains = <&cpg>; 56*8bab661aSEmmanuel Vadot resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; 57*8bab661aSEmmanuel Vadot interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; 58*8bab661aSEmmanuel Vadot }; 59*8bab661aSEmmanuel Vadot}; 60