1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2022 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-sev-kit-fabric.dtsi" 8 9/* Clock frequency (in Hz) of the rtcclk */ 10#define MTIMER_FREQ 1000000 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 model = "Microchip PolarFire-SoC SEV Kit"; 16 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs"; 17 18 aliases { 19 ethernet0 = &mac1; 20 serial0 = &mmuart0; 21 serial1 = &mmuart1; 22 serial2 = &mmuart2; 23 serial3 = &mmuart3; 24 serial4 = &mmuart4; 25 }; 26 27 chosen { 28 stdout-path = "serial1:115200n8"; 29 }; 30 31 cpus { 32 timebase-frequency = <MTIMER_FREQ>; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 fabricbuf0ddrc: buffer@80000000 { 41 compatible = "shared-dma-pool"; 42 reg = <0x0 0x80000000 0x0 0x2000000>; 43 }; 44 45 fabricbuf1ddrnc: buffer@c4000000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x0 0xc4000000 0x0 0x4000000>; 48 }; 49 50 fabricbuf2ddrncwcb: buffer@d4000000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x0 0xd4000000 0x0 0x4000000>; 53 }; 54 }; 55 56 ddrc_cache: memory@1000000000 { 57 device_type = "memory"; 58 reg = <0x10 0x0 0x0 0x76000000>; 59 }; 60}; 61 62&i2c0 { 63 status = "okay"; 64}; 65 66&gpio2 { 67 interrupts = <53>, <53>, <53>, <53>, 68 <53>, <53>, <53>, <53>, 69 <53>, <53>, <53>, <53>, 70 <53>, <53>, <53>, <53>, 71 <53>, <53>, <53>, <53>, 72 <53>, <53>, <53>, <53>, 73 <53>, <53>, <53>, <53>, 74 <53>, <53>, <53>, <53>; 75 status = "okay"; 76}; 77 78&mac0 { 79 status = "okay"; 80 phy-mode = "sgmii"; 81 phy-handle = <&phy0>; 82 phy1: ethernet-phy@9 { 83 reg = <9>; 84 }; 85 phy0: ethernet-phy@8 { 86 reg = <8>; 87 }; 88}; 89 90&mac1 { 91 status = "okay"; 92 phy-mode = "sgmii"; 93 phy-handle = <&phy1>; 94}; 95 96&mbox { 97 status = "okay"; 98}; 99 100&mmc { 101 status = "okay"; 102 bus-width = <4>; 103 disable-wp; 104 cap-sd-highspeed; 105 cap-mmc-highspeed; 106 mmc-ddr-1_8v; 107 mmc-hs200-1_8v; 108 sd-uhs-sdr12; 109 sd-uhs-sdr25; 110 sd-uhs-sdr50; 111 sd-uhs-sdr104; 112}; 113 114&mmuart1 { 115 status = "okay"; 116}; 117 118&mmuart2 { 119 status = "okay"; 120}; 121 122&mmuart3 { 123 status = "okay"; 124}; 125 126&mmuart4 { 127 status = "okay"; 128}; 129 130&refclk { 131 clock-frequency = <125000000>; 132}; 133 134&rtc { 135 status = "okay"; 136}; 137 138&syscontroller { 139 status = "okay"; 140}; 141 142&usb { 143 status = "okay"; 144 dr_mode = "otg"; 145}; 146