1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10 11/* Clock frequency (in Hz) of the rtcclk */ 12#define RTCCLK_FREQ 1000000 13 14/ { 15 model = "Microchip PolarFire-SoC Icicle Kit"; 16 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", 17 "microchip,mpfs"; 18 19 aliases { 20 ethernet0 = &mac1; 21 serial0 = &mmuart0; 22 serial1 = &mmuart1; 23 serial2 = &mmuart2; 24 serial3 = &mmuart3; 25 serial4 = &mmuart4; 26 }; 27 28 chosen { 29 stdout-path = "serial1:115200n8"; 30 }; 31 32 cpus { 33 timebase-frequency = <RTCCLK_FREQ>; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 39 led-1 { 40 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 41 color = <LED_COLOR_ID_RED>; 42 label = "led1"; 43 }; 44 45 led-2 { 46 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 47 color = <LED_COLOR_ID_RED>; 48 label = "led2"; 49 }; 50 51 led-3 { 52 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; 53 color = <LED_COLOR_ID_AMBER>; 54 label = "led3"; 55 }; 56 57 led-4 { 58 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 59 color = <LED_COLOR_ID_AMBER>; 60 label = "led4"; 61 }; 62 }; 63 64 ddrc_cache_lo: memory@80000000 { 65 device_type = "memory"; 66 reg = <0x0 0x80000000 0x0 0x40000000>; 67 status = "okay"; 68 }; 69 70 ddrc_cache_hi: memory@1040000000 { 71 device_type = "memory"; 72 reg = <0x10 0x40000000 0x0 0x40000000>; 73 status = "okay"; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hss_payload: region@BFC00000 { 82 reg = <0x0 0xBFC00000 0x0 0x400000>; 83 no-map; 84 }; 85 }; 86}; 87 88&core_pwm0 { 89 status = "okay"; 90}; 91 92&gpio2 { 93 interrupts = <53>, <53>, <53>, <53>, 94 <53>, <53>, <53>, <53>, 95 <53>, <53>, <53>, <53>, 96 <53>, <53>, <53>, <53>, 97 <53>, <53>, <53>, <53>, 98 <53>, <53>, <53>, <53>, 99 <53>, <53>, <53>, <53>, 100 <53>, <53>, <53>, <53>; 101 status = "okay"; 102}; 103 104&i2c0 { 105 status = "okay"; 106}; 107 108&i2c1 { 109 status = "okay"; 110}; 111 112&i2c2 { 113 status = "okay"; 114}; 115 116&mac0 { 117 phy-mode = "sgmii"; 118 phy-handle = <&phy0>; 119 status = "okay"; 120}; 121 122&mac1 { 123 phy-mode = "sgmii"; 124 phy-handle = <&phy1>; 125 status = "okay"; 126 127 phy1: ethernet-phy@9 { 128 reg = <9>; 129 }; 130 131 phy0: ethernet-phy@8 { 132 reg = <8>; 133 }; 134}; 135 136&mbox { 137 status = "okay"; 138}; 139 140&mmc { 141 bus-width = <4>; 142 disable-wp; 143 cap-sd-highspeed; 144 cap-mmc-highspeed; 145 mmc-ddr-1_8v; 146 mmc-hs200-1_8v; 147 sd-uhs-sdr12; 148 sd-uhs-sdr25; 149 sd-uhs-sdr50; 150 sd-uhs-sdr104; 151 status = "okay"; 152}; 153 154&mmuart1 { 155 status = "okay"; 156}; 157 158&mmuart2 { 159 status = "okay"; 160}; 161 162&mmuart3 { 163 status = "okay"; 164}; 165 166&mmuart4 { 167 status = "okay"; 168}; 169 170&pcie { 171 status = "okay"; 172}; 173 174&qspi { 175 status = "okay"; 176}; 177 178&refclk { 179 clock-frequency = <125000000>; 180}; 181 182&refclk_ccc { 183 clock-frequency = <50000000>; 184}; 185 186&rtc { 187 status = "okay"; 188}; 189 190&spi0 { 191 status = "okay"; 192}; 193 194&spi1 { 195 status = "okay"; 196}; 197 198&syscontroller { 199 status = "okay"; 200}; 201 202&usb { 203 status = "okay"; 204 dr_mode = "host"; 205}; 206