1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6#include "microchip-mpfs-fabric.dtsi" 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 model = "Microchip PolarFire SoC"; 12 compatible = "microchip,mpfs"; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 20 device_type = "cpu"; 21 i-cache-block-size = <64>; 22 i-cache-sets = <128>; 23 i-cache-size = <16384>; 24 reg = <0>; 25 riscv,isa = "rv64imac"; 26 clocks = <&clkcfg CLK_CPU>; 27 status = "disabled"; 28 29 cpu0_intc: interrupt-controller { 30 #interrupt-cells = <1>; 31 compatible = "riscv,cpu-intc"; 32 interrupt-controller; 33 }; 34 }; 35 36 cpu1: cpu@1 { 37 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 38 d-cache-block-size = <64>; 39 d-cache-sets = <64>; 40 d-cache-size = <32768>; 41 d-tlb-sets = <1>; 42 d-tlb-size = <32>; 43 device_type = "cpu"; 44 i-cache-block-size = <64>; 45 i-cache-sets = <64>; 46 i-cache-size = <32768>; 47 i-tlb-sets = <1>; 48 i-tlb-size = <32>; 49 mmu-type = "riscv,sv39"; 50 reg = <1>; 51 riscv,isa = "rv64imafdc"; 52 clocks = <&clkcfg CLK_CPU>; 53 tlb-split; 54 status = "okay"; 55 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 clocks = <&clkcfg CLK_CPU>; 80 tlb-split; 81 status = "okay"; 82 83 cpu2_intc: interrupt-controller { 84 #interrupt-cells = <1>; 85 compatible = "riscv,cpu-intc"; 86 interrupt-controller; 87 }; 88 }; 89 90 cpu3: cpu@3 { 91 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 92 d-cache-block-size = <64>; 93 d-cache-sets = <64>; 94 d-cache-size = <32768>; 95 d-tlb-sets = <1>; 96 d-tlb-size = <32>; 97 device_type = "cpu"; 98 i-cache-block-size = <64>; 99 i-cache-sets = <64>; 100 i-cache-size = <32768>; 101 i-tlb-sets = <1>; 102 i-tlb-size = <32>; 103 mmu-type = "riscv,sv39"; 104 reg = <3>; 105 riscv,isa = "rv64imafdc"; 106 clocks = <&clkcfg CLK_CPU>; 107 tlb-split; 108 status = "okay"; 109 110 cpu3_intc: interrupt-controller { 111 #interrupt-cells = <1>; 112 compatible = "riscv,cpu-intc"; 113 interrupt-controller; 114 }; 115 }; 116 117 cpu4: cpu@4 { 118 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 119 d-cache-block-size = <64>; 120 d-cache-sets = <64>; 121 d-cache-size = <32768>; 122 d-tlb-sets = <1>; 123 d-tlb-size = <32>; 124 device_type = "cpu"; 125 i-cache-block-size = <64>; 126 i-cache-sets = <64>; 127 i-cache-size = <32768>; 128 i-tlb-sets = <1>; 129 i-tlb-size = <32>; 130 mmu-type = "riscv,sv39"; 131 reg = <4>; 132 riscv,isa = "rv64imafdc"; 133 clocks = <&clkcfg CLK_CPU>; 134 tlb-split; 135 status = "okay"; 136 cpu4_intc: interrupt-controller { 137 #interrupt-cells = <1>; 138 compatible = "riscv,cpu-intc"; 139 interrupt-controller; 140 }; 141 }; 142 }; 143 144 refclk: mssrefclk { 145 compatible = "fixed-clock"; 146 #clock-cells = <0>; 147 }; 148 149 soc { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 compatible = "simple-bus"; 153 ranges; 154 155 cctrllr: cache-controller@2010000 { 156 compatible = "sifive,fu540-c000-ccache", "cache"; 157 reg = <0x0 0x2010000 0x0 0x1000>; 158 cache-block-size = <64>; 159 cache-level = <2>; 160 cache-sets = <1024>; 161 cache-size = <2097152>; 162 cache-unified; 163 interrupt-parent = <&plic>; 164 interrupts = <1>, <2>, <3>; 165 }; 166 167 clint: clint@2000000 { 168 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 169 reg = <0x0 0x2000000 0x0 0xC000>; 170 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 171 <&cpu1_intc 3>, <&cpu1_intc 7>, 172 <&cpu2_intc 3>, <&cpu2_intc 7>, 173 <&cpu3_intc 3>, <&cpu3_intc 7>, 174 <&cpu4_intc 3>, <&cpu4_intc 7>; 175 }; 176 177 plic: interrupt-controller@c000000 { 178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 179 reg = <0x0 0xc000000 0x0 0x4000000>; 180 #address-cells = <0>; 181 #interrupt-cells = <1>; 182 interrupt-controller; 183 interrupts-extended = <&cpu0_intc 11>, 184 <&cpu1_intc 11>, <&cpu1_intc 9>, 185 <&cpu2_intc 11>, <&cpu2_intc 9>, 186 <&cpu3_intc 11>, <&cpu3_intc 9>, 187 <&cpu4_intc 11>, <&cpu4_intc 9>; 188 riscv,ndev = <186>; 189 }; 190 191 clkcfg: clkcfg@20002000 { 192 compatible = "microchip,mpfs-clkcfg"; 193 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 194 clocks = <&refclk>; 195 #clock-cells = <1>; 196 }; 197 198 mmuart0: serial@20000000 { 199 compatible = "ns16550a"; 200 reg = <0x0 0x20000000 0x0 0x400>; 201 reg-io-width = <4>; 202 reg-shift = <2>; 203 interrupt-parent = <&plic>; 204 interrupts = <90>; 205 current-speed = <115200>; 206 clocks = <&clkcfg CLK_MMUART0>; 207 status = "disabled"; /* Reserved for the HSS */ 208 }; 209 210 mmuart1: serial@20100000 { 211 compatible = "ns16550a"; 212 reg = <0x0 0x20100000 0x0 0x400>; 213 reg-io-width = <4>; 214 reg-shift = <2>; 215 interrupt-parent = <&plic>; 216 interrupts = <91>; 217 current-speed = <115200>; 218 clocks = <&clkcfg CLK_MMUART1>; 219 status = "disabled"; 220 }; 221 222 mmuart2: serial@20102000 { 223 compatible = "ns16550a"; 224 reg = <0x0 0x20102000 0x0 0x400>; 225 reg-io-width = <4>; 226 reg-shift = <2>; 227 interrupt-parent = <&plic>; 228 interrupts = <92>; 229 current-speed = <115200>; 230 clocks = <&clkcfg CLK_MMUART2>; 231 status = "disabled"; 232 }; 233 234 mmuart3: serial@20104000 { 235 compatible = "ns16550a"; 236 reg = <0x0 0x20104000 0x0 0x400>; 237 reg-io-width = <4>; 238 reg-shift = <2>; 239 interrupt-parent = <&plic>; 240 interrupts = <93>; 241 current-speed = <115200>; 242 clocks = <&clkcfg CLK_MMUART3>; 243 status = "disabled"; 244 }; 245 246 mmuart4: serial@20106000 { 247 compatible = "ns16550a"; 248 reg = <0x0 0x20106000 0x0 0x400>; 249 reg-io-width = <4>; 250 reg-shift = <2>; 251 interrupt-parent = <&plic>; 252 interrupts = <94>; 253 clocks = <&clkcfg CLK_MMUART4>; 254 current-speed = <115200>; 255 status = "disabled"; 256 }; 257 258 /* Common node entry for emmc/sd */ 259 mmc: mmc@20008000 { 260 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 261 reg = <0x0 0x20008000 0x0 0x1000>; 262 interrupt-parent = <&plic>; 263 interrupts = <88>; 264 clocks = <&clkcfg CLK_MMC>; 265 max-frequency = <200000000>; 266 status = "disabled"; 267 }; 268 269 spi0: spi@20108000 { 270 compatible = "microchip,mpfs-spi"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 reg = <0x0 0x20108000 0x0 0x1000>; 274 interrupt-parent = <&plic>; 275 interrupts = <54>; 276 clocks = <&clkcfg CLK_SPI0>; 277 spi-max-frequency = <25000000>; 278 status = "disabled"; 279 }; 280 281 spi1: spi@20109000 { 282 compatible = "microchip,mpfs-spi"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 reg = <0x0 0x20109000 0x0 0x1000>; 286 interrupt-parent = <&plic>; 287 interrupts = <55>; 288 clocks = <&clkcfg CLK_SPI1>; 289 spi-max-frequency = <25000000>; 290 status = "disabled"; 291 }; 292 293 qspi: spi@21000000 { 294 compatible = "microchip,mpfs-qspi"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 reg = <0x0 0x21000000 0x0 0x1000>; 298 interrupt-parent = <&plic>; 299 interrupts = <85>; 300 clocks = <&clkcfg CLK_QSPI>; 301 spi-max-frequency = <25000000>; 302 status = "disabled"; 303 }; 304 305 i2c0: i2c@2010a000 { 306 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 307 reg = <0x0 0x2010a000 0x0 0x1000>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupt-parent = <&plic>; 311 interrupts = <58>; 312 clocks = <&clkcfg CLK_I2C0>; 313 clock-frequency = <100000>; 314 status = "disabled"; 315 }; 316 317 i2c1: i2c@2010b000 { 318 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 319 reg = <0x0 0x2010b000 0x0 0x1000>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 interrupt-parent = <&plic>; 323 interrupts = <61>; 324 clocks = <&clkcfg CLK_I2C1>; 325 clock-frequency = <100000>; 326 status = "disabled"; 327 }; 328 329 mac0: ethernet@20110000 { 330 compatible = "cdns,macb"; 331 reg = <0x0 0x20110000 0x0 0x2000>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 interrupt-parent = <&plic>; 335 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 336 local-mac-address = [00 00 00 00 00 00]; 337 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 338 clock-names = "pclk", "hclk"; 339 status = "disabled"; 340 }; 341 342 mac1: ethernet@20112000 { 343 compatible = "cdns,macb"; 344 reg = <0x0 0x20112000 0x0 0x2000>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 interrupt-parent = <&plic>; 348 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 349 local-mac-address = [00 00 00 00 00 00]; 350 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 351 clock-names = "pclk", "hclk"; 352 status = "disabled"; 353 }; 354 355 gpio0: gpio@20120000 { 356 compatible = "microchip,mpfs-gpio"; 357 reg = <0x0 0x20120000 0x0 0x1000>; 358 interrupt-parent = <&plic>; 359 interrupt-controller; 360 #interrupt-cells = <1>; 361 clocks = <&clkcfg CLK_GPIO0>; 362 gpio-controller; 363 #gpio-cells = <2>; 364 status = "disabled"; 365 }; 366 367 gpio1: gpio@20121000 { 368 compatible = "microchip,mpfs-gpio"; 369 reg = <0x0 0x20121000 0x0 0x1000>; 370 interrupt-parent = <&plic>; 371 interrupt-controller; 372 #interrupt-cells = <1>; 373 clocks = <&clkcfg CLK_GPIO1>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 status = "disabled"; 377 }; 378 379 gpio2: gpio@20122000 { 380 compatible = "microchip,mpfs-gpio"; 381 reg = <0x0 0x20122000 0x0 0x1000>; 382 interrupt-parent = <&plic>; 383 interrupt-controller; 384 #interrupt-cells = <1>; 385 clocks = <&clkcfg CLK_GPIO2>; 386 gpio-controller; 387 #gpio-cells = <2>; 388 status = "disabled"; 389 }; 390 391 rtc: rtc@20124000 { 392 compatible = "microchip,mpfs-rtc"; 393 reg = <0x0 0x20124000 0x0 0x1000>; 394 interrupt-parent = <&plic>; 395 interrupts = <80>, <81>; 396 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 397 clock-names = "rtc", "rtcref"; 398 status = "disabled"; 399 }; 400 401 usb: usb@20201000 { 402 compatible = "microchip,mpfs-musb"; 403 reg = <0x0 0x20201000 0x0 0x1000>; 404 interrupt-parent = <&plic>; 405 interrupts = <86>, <87>; 406 clocks = <&clkcfg CLK_USB>; 407 interrupt-names = "dma","mc"; 408 status = "disabled"; 409 }; 410 411 pcie: pcie@2000000000 { 412 compatible = "microchip,pcie-host-1.0"; 413 #address-cells = <0x3>; 414 #interrupt-cells = <0x1>; 415 #size-cells = <0x2>; 416 device_type = "pci"; 417 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 418 reg-names = "cfg", "apb"; 419 bus-range = <0x0 0x7f>; 420 interrupt-parent = <&plic>; 421 interrupts = <119>; 422 interrupt-map = <0 0 0 1 &pcie_intc 0>, 423 <0 0 0 2 &pcie_intc 1>, 424 <0 0 0 3 &pcie_intc 2>, 425 <0 0 0 4 &pcie_intc 3>; 426 interrupt-map-mask = <0 0 0 7>; 427 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; 428 clock-names = "fic0", "fic1", "fic3"; 429 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; 430 msi-parent = <&pcie>; 431 msi-controller; 432 microchip,axi-m-atr0 = <0x10 0x0>; 433 status = "disabled"; 434 pcie_intc: legacy-interrupt-controller { 435 #address-cells = <0>; 436 #interrupt-cells = <1>; 437 interrupt-controller; 438 }; 439 }; 440 441 mbox: mailbox@37020000 { 442 compatible = "microchip,mpfs-mailbox"; 443 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 444 interrupt-parent = <&plic>; 445 interrupts = <96>; 446 #mbox-cells = <1>; 447 status = "disabled"; 448 }; 449 450 syscontroller: syscontroller { 451 compatible = "microchip,mpfs-sys-controller"; 452 mboxes = <&mbox 0>; 453 }; 454 }; 455}; 456