1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 clk_pg11_pin: clk-pg11-pin { 57 pins = "PG11"; 58 function = "clk"; 59 }; 60 61 /omit-if-no-ref/ 62 dsi_4lane_pins: dsi-4lane-pins { 63 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 64 "PD6", "PD7", "PD8", "PD9"; 65 drive-strength = <30>; 66 function = "dsi"; 67 }; 68 69 /omit-if-no-ref/ 70 lcd_rgb666_pins: lcd-rgb666-pins { 71 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 72 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 73 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 74 "PD18", "PD19", "PD20", "PD21"; 75 function = "lcd0"; 76 }; 77 78 /omit-if-no-ref/ 79 mmc0_pins: mmc0-pins { 80 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 81 function = "mmc0"; 82 }; 83 84 /omit-if-no-ref/ 85 mmc1_pins: mmc1-pins { 86 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 87 function = "mmc1"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc2_pins: mmc2-pins { 92 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 93 function = "mmc2"; 94 }; 95 96 /omit-if-no-ref/ 97 rgmii_pe_pins: rgmii-pe-pins { 98 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 99 "PE5", "PE6", "PE7", "PE8", "PE9", 100 "PE11", "PE12", "PE13", "PE14", "PE15"; 101 function = "emac"; 102 }; 103 104 /omit-if-no-ref/ 105 rmii_pe_pins: rmii-pe-pins { 106 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 107 "PE5", "PE6", "PE7", "PE8", "PE9"; 108 function = "emac"; 109 }; 110 111 /omit-if-no-ref/ 112 spi0_pins: spi0-pins { 113 pins = "PC2", "PC3", "PC4", "PC5"; 114 function = "spi0"; 115 }; 116 117 /omit-if-no-ref/ 118 uart1_pg6_pins: uart1-pg6-pins { 119 pins = "PG6", "PG7"; 120 function = "uart1"; 121 }; 122 123 /omit-if-no-ref/ 124 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 125 pins = "PG8", "PG9"; 126 function = "uart1"; 127 }; 128 129 /omit-if-no-ref/ 130 uart3_pb_pins: uart3-pb-pins { 131 pins = "PB6", "PB7"; 132 function = "uart3"; 133 }; 134 }; 135 136 ccu: clock-controller@2001000 { 137 compatible = "allwinner,sun20i-d1-ccu"; 138 reg = <0x2001000 0x1000>; 139 clocks = <&dcxo>, 140 <&rtc CLK_OSC32K>, 141 <&rtc CLK_IOSC>; 142 clock-names = "hosc", "losc", "iosc"; 143 #clock-cells = <1>; 144 #reset-cells = <1>; 145 }; 146 147 dmic: dmic@2031000 { 148 compatible = "allwinner,sun20i-d1-dmic", 149 "allwinner,sun50i-h6-dmic"; 150 reg = <0x2031000 0x400>; 151 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&ccu CLK_BUS_DMIC>, 153 <&ccu CLK_DMIC>; 154 clock-names = "bus", "mod"; 155 resets = <&ccu RST_BUS_DMIC>; 156 dmas = <&dma 8>; 157 dma-names = "rx"; 158 status = "disabled"; 159 #sound-dai-cells = <0>; 160 }; 161 162 i2s1: i2s@2033000 { 163 compatible = "allwinner,sun20i-d1-i2s", 164 "allwinner,sun50i-r329-i2s"; 165 reg = <0x2033000 0x1000>; 166 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&ccu CLK_BUS_I2S1>, 168 <&ccu CLK_I2S1>; 169 clock-names = "apb", "mod"; 170 resets = <&ccu RST_BUS_I2S1>; 171 dmas = <&dma 4>, <&dma 4>; 172 dma-names = "rx", "tx"; 173 status = "disabled"; 174 #sound-dai-cells = <0>; 175 }; 176 177 i2s2: i2s@2034000 { 178 compatible = "allwinner,sun20i-d1-i2s", 179 "allwinner,sun50i-r329-i2s"; 180 reg = <0x2034000 0x1000>; 181 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&ccu CLK_BUS_I2S2>, 183 <&ccu CLK_I2S2>; 184 clock-names = "apb", "mod"; 185 resets = <&ccu RST_BUS_I2S2>; 186 dmas = <&dma 5>, <&dma 5>; 187 dma-names = "rx", "tx"; 188 status = "disabled"; 189 #sound-dai-cells = <0>; 190 }; 191 192 timer: timer@2050000 { 193 compatible = "allwinner,sun20i-d1-timer", 194 "allwinner,sun8i-a23-timer"; 195 reg = <0x2050000 0xa0>; 196 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 197 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&dcxo>; 199 }; 200 201 wdt: watchdog@20500a0 { 202 compatible = "allwinner,sun20i-d1-wdt-reset", 203 "allwinner,sun20i-d1-wdt"; 204 reg = <0x20500a0 0x20>; 205 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 207 clock-names = "hosc", "losc"; 208 status = "reserved"; 209 }; 210 211 uart0: serial@2500000 { 212 compatible = "snps,dw-apb-uart"; 213 reg = <0x2500000 0x400>; 214 reg-io-width = <4>; 215 reg-shift = <2>; 216 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&ccu CLK_BUS_UART0>; 218 resets = <&ccu RST_BUS_UART0>; 219 dmas = <&dma 14>, <&dma 14>; 220 dma-names = "tx", "rx"; 221 status = "disabled"; 222 }; 223 224 uart1: serial@2500400 { 225 compatible = "snps,dw-apb-uart"; 226 reg = <0x2500400 0x400>; 227 reg-io-width = <4>; 228 reg-shift = <2>; 229 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&ccu CLK_BUS_UART1>; 231 resets = <&ccu RST_BUS_UART1>; 232 dmas = <&dma 15>, <&dma 15>; 233 dma-names = "tx", "rx"; 234 status = "disabled"; 235 }; 236 237 uart2: serial@2500800 { 238 compatible = "snps,dw-apb-uart"; 239 reg = <0x2500800 0x400>; 240 reg-io-width = <4>; 241 reg-shift = <2>; 242 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&ccu CLK_BUS_UART2>; 244 resets = <&ccu RST_BUS_UART2>; 245 dmas = <&dma 16>, <&dma 16>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 uart3: serial@2500c00 { 251 compatible = "snps,dw-apb-uart"; 252 reg = <0x2500c00 0x400>; 253 reg-io-width = <4>; 254 reg-shift = <2>; 255 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&ccu CLK_BUS_UART3>; 257 resets = <&ccu RST_BUS_UART3>; 258 dmas = <&dma 17>, <&dma 17>; 259 dma-names = "tx", "rx"; 260 status = "disabled"; 261 }; 262 263 uart4: serial@2501000 { 264 compatible = "snps,dw-apb-uart"; 265 reg = <0x2501000 0x400>; 266 reg-io-width = <4>; 267 reg-shift = <2>; 268 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&ccu CLK_BUS_UART4>; 270 resets = <&ccu RST_BUS_UART4>; 271 dmas = <&dma 18>, <&dma 18>; 272 dma-names = "tx", "rx"; 273 status = "disabled"; 274 }; 275 276 uart5: serial@2501400 { 277 compatible = "snps,dw-apb-uart"; 278 reg = <0x2501400 0x400>; 279 reg-io-width = <4>; 280 reg-shift = <2>; 281 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&ccu CLK_BUS_UART5>; 283 resets = <&ccu RST_BUS_UART5>; 284 dmas = <&dma 19>, <&dma 19>; 285 dma-names = "tx", "rx"; 286 status = "disabled"; 287 }; 288 289 i2c0: i2c@2502000 { 290 compatible = "allwinner,sun20i-d1-i2c", 291 "allwinner,sun8i-v536-i2c", 292 "allwinner,sun6i-a31-i2c"; 293 reg = <0x2502000 0x400>; 294 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&ccu CLK_BUS_I2C0>; 296 resets = <&ccu RST_BUS_I2C0>; 297 dmas = <&dma 43>, <&dma 43>; 298 dma-names = "rx", "tx"; 299 status = "disabled"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 }; 303 304 i2c1: i2c@2502400 { 305 compatible = "allwinner,sun20i-d1-i2c", 306 "allwinner,sun8i-v536-i2c", 307 "allwinner,sun6i-a31-i2c"; 308 reg = <0x2502400 0x400>; 309 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&ccu CLK_BUS_I2C1>; 311 resets = <&ccu RST_BUS_I2C1>; 312 dmas = <&dma 44>, <&dma 44>; 313 dma-names = "rx", "tx"; 314 status = "disabled"; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 }; 318 319 i2c2: i2c@2502800 { 320 compatible = "allwinner,sun20i-d1-i2c", 321 "allwinner,sun8i-v536-i2c", 322 "allwinner,sun6i-a31-i2c"; 323 reg = <0x2502800 0x400>; 324 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&ccu CLK_BUS_I2C2>; 326 resets = <&ccu RST_BUS_I2C2>; 327 dmas = <&dma 45>, <&dma 45>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 }; 333 334 i2c3: i2c@2502c00 { 335 compatible = "allwinner,sun20i-d1-i2c", 336 "allwinner,sun8i-v536-i2c", 337 "allwinner,sun6i-a31-i2c"; 338 reg = <0x2502c00 0x400>; 339 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&ccu CLK_BUS_I2C3>; 341 resets = <&ccu RST_BUS_I2C3>; 342 dmas = <&dma 46>, <&dma 46>; 343 dma-names = "rx", "tx"; 344 status = "disabled"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 }; 348 349 syscon: syscon@3000000 { 350 compatible = "allwinner,sun20i-d1-system-control"; 351 reg = <0x3000000 0x1000>; 352 ranges; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 }; 356 357 dma: dma-controller@3002000 { 358 compatible = "allwinner,sun20i-d1-dma"; 359 reg = <0x3002000 0x1000>; 360 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 362 clock-names = "bus", "mbus"; 363 resets = <&ccu RST_BUS_DMA>; 364 dma-channels = <16>; 365 dma-requests = <48>; 366 #dma-cells = <1>; 367 }; 368 369 sid: efuse@3006000 { 370 compatible = "allwinner,sun20i-d1-sid"; 371 reg = <0x3006000 0x1000>; 372 #address-cells = <1>; 373 #size-cells = <1>; 374 }; 375 376 crypto: crypto@3040000 { 377 compatible = "allwinner,sun20i-d1-crypto"; 378 reg = <0x3040000 0x800>; 379 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&ccu CLK_BUS_CE>, 381 <&ccu CLK_CE>, 382 <&ccu CLK_MBUS_CE>, 383 <&rtc CLK_IOSC>; 384 clock-names = "bus", "mod", "ram", "trng"; 385 resets = <&ccu RST_BUS_CE>; 386 }; 387 388 mbus: dram-controller@3102000 { 389 compatible = "allwinner,sun20i-d1-mbus"; 390 reg = <0x3102000 0x1000>, 391 <0x3103000 0x1000>; 392 reg-names = "mbus", "dram"; 393 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_MBUS>, 395 <&ccu CLK_DRAM>, 396 <&ccu CLK_BUS_DRAM>; 397 clock-names = "mbus", "dram", "bus"; 398 dma-ranges = <0 0x40000000 0x80000000>; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 #interconnect-cells = <1>; 402 }; 403 404 mmc0: mmc@4020000 { 405 compatible = "allwinner,sun20i-d1-mmc"; 406 reg = <0x4020000 0x1000>; 407 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 409 clock-names = "ahb", "mmc"; 410 resets = <&ccu RST_BUS_MMC0>; 411 reset-names = "ahb"; 412 cap-sd-highspeed; 413 max-frequency = <150000000>; 414 no-mmc; 415 status = "disabled"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 }; 419 420 mmc1: mmc@4021000 { 421 compatible = "allwinner,sun20i-d1-mmc"; 422 reg = <0x4021000 0x1000>; 423 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 425 clock-names = "ahb", "mmc"; 426 resets = <&ccu RST_BUS_MMC1>; 427 reset-names = "ahb"; 428 cap-sd-highspeed; 429 max-frequency = <150000000>; 430 no-mmc; 431 status = "disabled"; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 }; 435 436 mmc2: mmc@4022000 { 437 compatible = "allwinner,sun20i-d1-emmc", 438 "allwinner,sun50i-a100-emmc"; 439 reg = <0x4022000 0x1000>; 440 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 442 clock-names = "ahb", "mmc"; 443 resets = <&ccu RST_BUS_MMC2>; 444 reset-names = "ahb"; 445 cap-mmc-highspeed; 446 max-frequency = <150000000>; 447 mmc-ddr-1_8v; 448 mmc-ddr-3_3v; 449 no-sd; 450 no-sdio; 451 status = "disabled"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 }; 455 456 spi0: spi@4025000 { 457 compatible = "allwinner,sun20i-d1-spi", 458 "allwinner,sun50i-r329-spi"; 459 reg = <0x04025000 0x1000>; 460 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 462 clock-names = "ahb", "mod"; 463 dmas = <&dma 22>, <&dma 22>; 464 dma-names = "rx", "tx"; 465 resets = <&ccu RST_BUS_SPI0>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 spi1: spi@4026000 { 472 compatible = "allwinner,sun20i-d1-spi-dbi", 473 "allwinner,sun50i-r329-spi-dbi", 474 "allwinner,sun50i-r329-spi"; 475 reg = <0x04026000 0x1000>; 476 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 478 clock-names = "ahb", "mod"; 479 dmas = <&dma 23>, <&dma 23>; 480 dma-names = "rx", "tx"; 481 resets = <&ccu RST_BUS_SPI1>; 482 status = "disabled"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 }; 486 487 usb_otg: usb@4100000 { 488 compatible = "allwinner,sun20i-d1-musb", 489 "allwinner,sun8i-a33-musb"; 490 reg = <0x4100000 0x400>; 491 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "mc"; 493 clocks = <&ccu CLK_BUS_OTG>; 494 resets = <&ccu RST_BUS_OTG>; 495 extcon = <&usbphy 0>; 496 phys = <&usbphy 0>; 497 phy-names = "usb"; 498 status = "disabled"; 499 }; 500 501 usbphy: phy@4100400 { 502 compatible = "allwinner,sun20i-d1-usb-phy"; 503 reg = <0x4100400 0x100>, 504 <0x4101800 0x100>, 505 <0x4200800 0x100>; 506 reg-names = "phy_ctrl", 507 "pmu0", 508 "pmu1"; 509 clocks = <&dcxo>, 510 <&dcxo>; 511 clock-names = "usb0_phy", 512 "usb1_phy"; 513 resets = <&ccu RST_USB_PHY0>, 514 <&ccu RST_USB_PHY1>; 515 reset-names = "usb0_reset", 516 "usb1_reset"; 517 status = "disabled"; 518 #phy-cells = <1>; 519 }; 520 521 ehci0: usb@4101000 { 522 compatible = "allwinner,sun20i-d1-ehci", 523 "generic-ehci"; 524 reg = <0x4101000 0x100>; 525 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&ccu CLK_BUS_OHCI0>, 527 <&ccu CLK_BUS_EHCI0>, 528 <&ccu CLK_USB_OHCI0>; 529 resets = <&ccu RST_BUS_OHCI0>, 530 <&ccu RST_BUS_EHCI0>; 531 phys = <&usbphy 0>; 532 phy-names = "usb"; 533 status = "disabled"; 534 }; 535 536 ohci0: usb@4101400 { 537 compatible = "allwinner,sun20i-d1-ohci", 538 "generic-ohci"; 539 reg = <0x4101400 0x100>; 540 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&ccu CLK_BUS_OHCI0>, 542 <&ccu CLK_USB_OHCI0>; 543 resets = <&ccu RST_BUS_OHCI0>; 544 phys = <&usbphy 0>; 545 phy-names = "usb"; 546 status = "disabled"; 547 }; 548 549 ehci1: usb@4200000 { 550 compatible = "allwinner,sun20i-d1-ehci", 551 "generic-ehci"; 552 reg = <0x4200000 0x100>; 553 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&ccu CLK_BUS_OHCI1>, 555 <&ccu CLK_BUS_EHCI1>, 556 <&ccu CLK_USB_OHCI1>; 557 resets = <&ccu RST_BUS_OHCI1>, 558 <&ccu RST_BUS_EHCI1>; 559 phys = <&usbphy 1>; 560 phy-names = "usb"; 561 status = "disabled"; 562 }; 563 564 ohci1: usb@4200400 { 565 compatible = "allwinner,sun20i-d1-ohci", 566 "generic-ohci"; 567 reg = <0x4200400 0x100>; 568 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&ccu CLK_BUS_OHCI1>, 570 <&ccu CLK_USB_OHCI1>; 571 resets = <&ccu RST_BUS_OHCI1>; 572 phys = <&usbphy 1>; 573 phy-names = "usb"; 574 status = "disabled"; 575 }; 576 577 emac: ethernet@4500000 { 578 compatible = "allwinner,sun20i-d1-emac", 579 "allwinner,sun50i-a64-emac"; 580 reg = <0x4500000 0x10000>; 581 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "macirq"; 583 clocks = <&ccu CLK_BUS_EMAC>; 584 clock-names = "stmmaceth"; 585 resets = <&ccu RST_BUS_EMAC>; 586 reset-names = "stmmaceth"; 587 syscon = <&syscon>; 588 status = "disabled"; 589 590 mdio: mdio { 591 compatible = "snps,dwmac-mdio"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 }; 595 }; 596 597 display_clocks: clock-controller@5000000 { 598 compatible = "allwinner,sun20i-d1-de2-clk", 599 "allwinner,sun50i-h5-de2-clk"; 600 reg = <0x5000000 0x10000>; 601 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 602 clock-names = "bus", "mod"; 603 resets = <&ccu RST_BUS_DE>; 604 #clock-cells = <1>; 605 #reset-cells = <1>; 606 }; 607 608 mixer0: mixer@5100000 { 609 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 610 reg = <0x5100000 0x100000>; 611 clocks = <&display_clocks CLK_BUS_MIXER0>, 612 <&display_clocks CLK_MIXER0>; 613 clock-names = "bus", "mod"; 614 resets = <&display_clocks RST_MIXER0>; 615 616 ports { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 620 mixer0_out: port@1 { 621 reg = <1>; 622 623 mixer0_out_tcon_top_mixer0: endpoint { 624 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 625 }; 626 }; 627 }; 628 }; 629 630 mixer1: mixer@5200000 { 631 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 632 reg = <0x5200000 0x100000>; 633 clocks = <&display_clocks CLK_BUS_MIXER1>, 634 <&display_clocks CLK_MIXER1>; 635 clock-names = "bus", "mod"; 636 resets = <&display_clocks RST_MIXER1>; 637 638 ports { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 mixer1_out: port@1 { 643 reg = <1>; 644 645 mixer1_out_tcon_top_mixer1: endpoint { 646 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 647 }; 648 }; 649 }; 650 }; 651 652 dsi: dsi@5450000 { 653 compatible = "allwinner,sun20i-d1-mipi-dsi", 654 "allwinner,sun50i-a100-mipi-dsi"; 655 reg = <0x5450000 0x1000>; 656 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&ccu CLK_BUS_MIPI_DSI>, 658 <&tcon_top CLK_TCON_TOP_DSI>; 659 clock-names = "bus", "mod"; 660 resets = <&ccu RST_BUS_MIPI_DSI>; 661 phys = <&dphy>; 662 phy-names = "dphy"; 663 status = "disabled"; 664 665 port { 666 dsi_in_tcon_lcd0: endpoint { 667 remote-endpoint = <&tcon_lcd0_out_dsi>; 668 }; 669 }; 670 }; 671 672 dphy: phy@5451000 { 673 compatible = "allwinner,sun20i-d1-mipi-dphy", 674 "allwinner,sun50i-a100-mipi-dphy"; 675 reg = <0x5451000 0x1000>; 676 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&ccu CLK_BUS_MIPI_DSI>, 678 <&ccu CLK_MIPI_DSI>; 679 clock-names = "bus", "mod"; 680 resets = <&ccu RST_BUS_MIPI_DSI>; 681 #phy-cells = <0>; 682 }; 683 684 tcon_top: tcon-top@5460000 { 685 compatible = "allwinner,sun20i-d1-tcon-top"; 686 reg = <0x5460000 0x1000>; 687 clocks = <&ccu CLK_BUS_DPSS_TOP>, 688 <&ccu CLK_TCON_TV>, 689 <&ccu CLK_TVE>, 690 <&ccu CLK_TCON_LCD0>; 691 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 692 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 693 resets = <&ccu RST_BUS_DPSS_TOP>; 694 #clock-cells = <1>; 695 696 ports { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 tcon_top_mixer0_in: port@0 { 701 reg = <0>; 702 703 tcon_top_mixer0_in_mixer0: endpoint { 704 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 705 }; 706 }; 707 708 tcon_top_mixer0_out: port@1 { 709 reg = <1>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 714 reg = <0>; 715 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 716 }; 717 718 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 719 reg = <2>; 720 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 721 }; 722 }; 723 724 tcon_top_mixer1_in: port@2 { 725 reg = <2>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 729 tcon_top_mixer1_in_mixer1: endpoint@1 { 730 reg = <1>; 731 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 732 }; 733 }; 734 735 tcon_top_mixer1_out: port@3 { 736 reg = <3>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 740 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 741 reg = <0>; 742 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 743 }; 744 745 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 746 reg = <2>; 747 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 748 }; 749 }; 750 751 tcon_top_hdmi_in: port@4 { 752 reg = <4>; 753 754 tcon_top_hdmi_in_tcon_tv0: endpoint { 755 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 756 }; 757 }; 758 759 tcon_top_hdmi_out: port@5 { 760 reg = <5>; 761 }; 762 }; 763 }; 764 765 tcon_lcd0: lcd-controller@5461000 { 766 compatible = "allwinner,sun20i-d1-tcon-lcd"; 767 reg = <0x5461000 0x1000>; 768 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&ccu CLK_BUS_TCON_LCD0>, 770 <&ccu CLK_TCON_LCD0>; 771 clock-names = "ahb", "tcon-ch0"; 772 clock-output-names = "tcon-pixel-clock"; 773 resets = <&ccu RST_BUS_TCON_LCD0>, 774 <&ccu RST_BUS_LVDS0>; 775 reset-names = "lcd", "lvds"; 776 #clock-cells = <0>; 777 778 ports { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 tcon_lcd0_in: port@0 { 783 reg = <0>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 788 reg = <0>; 789 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 790 }; 791 792 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 793 reg = <1>; 794 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 795 }; 796 }; 797 798 tcon_lcd0_out: port@1 { 799 reg = <1>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 803 tcon_lcd0_out_dsi: endpoint@1 { 804 reg = <1>; 805 remote-endpoint = <&dsi_in_tcon_lcd0>; 806 }; 807 }; 808 }; 809 }; 810 811 tcon_tv0: lcd-controller@5470000 { 812 compatible = "allwinner,sun20i-d1-tcon-tv"; 813 reg = <0x5470000 0x1000>; 814 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&ccu CLK_BUS_TCON_TV>, 816 <&tcon_top CLK_TCON_TOP_TV0>; 817 clock-names = "ahb", "tcon-ch1"; 818 resets = <&ccu RST_BUS_TCON_TV>; 819 reset-names = "lcd"; 820 821 ports { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 825 tcon_tv0_in: port@0 { 826 reg = <0>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 831 reg = <0>; 832 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 833 }; 834 835 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 836 reg = <1>; 837 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 838 }; 839 }; 840 841 tcon_tv0_out: port@1 { 842 reg = <1>; 843 844 tcon_tv0_out_tcon_top_hdmi: endpoint { 845 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 846 }; 847 }; 848 }; 849 }; 850 851 ppu: power-controller@7001000 { 852 compatible = "allwinner,sun20i-d1-ppu"; 853 reg = <0x7001000 0x1000>; 854 clocks = <&r_ccu CLK_BUS_R_PPU>; 855 resets = <&r_ccu RST_BUS_R_PPU>; 856 #power-domain-cells = <1>; 857 }; 858 859 r_ccu: clock-controller@7010000 { 860 compatible = "allwinner,sun20i-d1-r-ccu"; 861 reg = <0x7010000 0x400>; 862 clocks = <&dcxo>, 863 <&rtc CLK_OSC32K>, 864 <&rtc CLK_IOSC>, 865 <&ccu CLK_PLL_PERIPH0_DIV3>; 866 clock-names = "hosc", "losc", "iosc", "pll-periph"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 }; 870 871 rtc: rtc@7090000 { 872 compatible = "allwinner,sun20i-d1-rtc", 873 "allwinner,sun50i-r329-rtc"; 874 reg = <0x7090000 0x400>; 875 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&r_ccu CLK_BUS_R_RTC>, 877 <&dcxo>, 878 <&r_ccu CLK_R_AHB>; 879 clock-names = "bus", "hosc", "ahb"; 880 #clock-cells = <1>; 881 }; 882 }; 883}; 884