1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#define SOC_PERIPHERAL_IRQ(nr) (nr + 16) 5 6#include "sunxi-d1s-t113.dtsi" 7 8/ { 9 cpus { 10 timebase-frequency = <24000000>; 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu0: cpu@0 { 15 compatible = "thead,c906", "riscv"; 16 device_type = "cpu"; 17 reg = <0>; 18 clocks = <&ccu CLK_RISCV>; 19 d-cache-block-size = <64>; 20 d-cache-sets = <256>; 21 d-cache-size = <32768>; 22 i-cache-block-size = <64>; 23 i-cache-sets = <128>; 24 i-cache-size = <32768>; 25 mmu-type = "riscv,sv39"; 26 operating-points-v2 = <&opp_table_cpu>; 27 riscv,isa = "rv64imafdc"; 28 #cooling-cells = <2>; 29 30 cpu0_intc: interrupt-controller { 31 compatible = "riscv,cpu-intc"; 32 interrupt-controller; 33 #address-cells = <0>; 34 #interrupt-cells = <1>; 35 }; 36 }; 37 }; 38 39 opp_table_cpu: opp-table-cpu { 40 compatible = "operating-points-v2"; 41 42 opp-408000000 { 43 opp-hz = /bits/ 64 <408000000>; 44 opp-microvolt = <900000 900000 1100000>; 45 }; 46 47 opp-1080000000 { 48 opp-hz = /bits/ 64 <1008000000>; 49 opp-microvolt = <900000 900000 1100000>; 50 }; 51 }; 52 53 soc { 54 interrupt-parent = <&plic>; 55 56 riscv_wdt: watchdog@6011000 { 57 compatible = "allwinner,sun20i-d1-wdt"; 58 reg = <0x6011000 0x20>; 59 interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>; 60 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 61 clock-names = "hosc", "losc"; 62 }; 63 64 plic: interrupt-controller@10000000 { 65 compatible = "allwinner,sun20i-d1-plic", 66 "thead,c900-plic"; 67 reg = <0x10000000 0x4000000>; 68 interrupts-extended = <&cpu0_intc 11>, 69 <&cpu0_intc 9>; 70 interrupt-controller; 71 riscv,ndev = <175>; 72 #address-cells = <0>; 73 #interrupt-cells = <2>; 74 }; 75 }; 76}; 77