1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * STX GP3 - 8560 ADS Device Tree Source 4 * 5 * Copyright 2008 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9 10/include/ "fsl/e500v1_power_isa.dtsi" 11 12/ { 13 model = "stx,gp3"; 14 compatible = "stx,gp3-8560", "stx,gp3"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 ethernet0 = &enet0; 20 ethernet1 = &enet1; 21 serial0 = &serial0; 22 pci0 = &pci0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8560@0 { 30 device_type = "cpu"; 31 reg = <0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <32768>; 35 i-cache-size = <32768>; 36 timebase-frequency = <0>; 37 bus-frequency = <0>; 38 clock-frequency = <0>; 39 next-level-cache = <&L2>; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x00000000 0x10000000>; 46 }; 47 48 soc@fdf00000 { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 device_type = "soc"; 52 ranges = <0 0xfdf00000 0x100000>; 53 bus-frequency = <0>; 54 compatible = "fsl,mpc8560-immr", "simple-bus"; 55 56 ecm-law@0 { 57 compatible = "fsl,ecm-law"; 58 reg = <0x0 0x1000>; 59 fsl,num-laws = <8>; 60 }; 61 62 ecm@1000 { 63 compatible = "fsl,mpc8560-ecm", "fsl,ecm"; 64 reg = <0x1000 0x1000>; 65 interrupts = <17 2>; 66 interrupt-parent = <&mpic>; 67 }; 68 69 memory-controller@2000 { 70 compatible = "fsl,mpc8540-memory-controller"; 71 reg = <0x2000 0x1000>; 72 interrupt-parent = <&mpic>; 73 interrupts = <18 2>; 74 }; 75 76 L2: l2-cache-controller@20000 { 77 compatible = "fsl,mpc8540-l2-cache-controller"; 78 reg = <0x20000 0x1000>; 79 cache-line-size = <32>; 80 cache-size = <0x40000>; // L2, 256K 81 interrupt-parent = <&mpic>; 82 interrupts = <16 2>; 83 }; 84 85 i2c@3000 { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 cell-index = <0>; 89 compatible = "fsl-i2c"; 90 reg = <0x3000 0x100>; 91 interrupts = <43 2>; 92 interrupt-parent = <&mpic>; 93 dfsrr; 94 }; 95 96 dma@21300 { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; 100 reg = <0x21300 0x4>; 101 ranges = <0x0 0x21100 0x200>; 102 cell-index = <0>; 103 dma-channel@0 { 104 compatible = "fsl,mpc8560-dma-channel", 105 "fsl,eloplus-dma-channel"; 106 reg = <0x0 0x80>; 107 cell-index = <0>; 108 interrupt-parent = <&mpic>; 109 interrupts = <20 2>; 110 }; 111 dma-channel@80 { 112 compatible = "fsl,mpc8560-dma-channel", 113 "fsl,eloplus-dma-channel"; 114 reg = <0x80 0x80>; 115 cell-index = <1>; 116 interrupt-parent = <&mpic>; 117 interrupts = <21 2>; 118 }; 119 dma-channel@100 { 120 compatible = "fsl,mpc8560-dma-channel", 121 "fsl,eloplus-dma-channel"; 122 reg = <0x100 0x80>; 123 cell-index = <2>; 124 interrupt-parent = <&mpic>; 125 interrupts = <22 2>; 126 }; 127 dma-channel@180 { 128 compatible = "fsl,mpc8560-dma-channel", 129 "fsl,eloplus-dma-channel"; 130 reg = <0x180 0x80>; 131 cell-index = <3>; 132 interrupt-parent = <&mpic>; 133 interrupts = <23 2>; 134 }; 135 }; 136 137 enet0: ethernet@24000 { 138 #address-cells = <1>; 139 #size-cells = <1>; 140 cell-index = <0>; 141 device_type = "network"; 142 model = "TSEC"; 143 compatible = "gianfar"; 144 reg = <0x24000 0x1000>; 145 ranges = <0x0 0x24000 0x1000>; 146 local-mac-address = [ 00 00 00 00 00 00 ]; 147 interrupts = <29 2 30 2 34 2>; 148 interrupt-parent = <&mpic>; 149 tbi-handle = <&tbi0>; 150 phy-handle = <&phy2>; 151 152 mdio@520 { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 compatible = "fsl,gianfar-mdio"; 156 reg = <0x520 0x20>; 157 158 phy2: ethernet-phy@2 { 159 interrupt-parent = <&mpic>; 160 interrupts = <5 4>; 161 reg = <2>; 162 }; 163 phy4: ethernet-phy@4 { 164 interrupt-parent = <&mpic>; 165 interrupts = <5 4>; 166 reg = <4>; 167 }; 168 tbi0: tbi-phy@11 { 169 reg = <0x11>; 170 device_type = "tbi-phy"; 171 }; 172 }; 173 }; 174 175 enet1: ethernet@25000 { 176 #address-cells = <1>; 177 #size-cells = <1>; 178 cell-index = <1>; 179 device_type = "network"; 180 model = "TSEC"; 181 compatible = "gianfar"; 182 reg = <0x25000 0x1000>; 183 ranges = <0x0 0x25000 0x1000>; 184 local-mac-address = [ 00 00 00 00 00 00 ]; 185 interrupts = <35 2 36 2 40 2>; 186 interrupt-parent = <&mpic>; 187 tbi-handle = <&tbi1>; 188 phy-handle = <&phy4>; 189 190 mdio@520 { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 compatible = "fsl,gianfar-tbi"; 194 reg = <0x520 0x20>; 195 196 tbi1: tbi-phy@11 { 197 reg = <0x11>; 198 device_type = "tbi-phy"; 199 }; 200 }; 201 }; 202 203 mpic: pic@40000 { 204 interrupt-controller; 205 #address-cells = <0>; 206 #interrupt-cells = <2>; 207 reg = <0x40000 0x40000>; 208 compatible = "chrp,open-pic"; 209 device_type = "open-pic"; 210 }; 211 212 cpm@919c0 { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; 216 reg = <0x919c0 0x30>; 217 ranges; 218 219 muram@80000 { 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0 0x80000 0x10000>; 223 224 data@0 { 225 compatible = "fsl,cpm-muram-data"; 226 reg = <0 0x4000 0x9000 0x2000>; 227 }; 228 }; 229 230 brg@919f0 { 231 compatible = "fsl,mpc8560-brg", 232 "fsl,cpm2-brg", 233 "fsl,cpm-brg"; 234 reg = <0x919f0 0x10 0x915f0 0x10>; 235 clock-frequency = <0>; 236 }; 237 238 cpmpic: pic@90c00 { 239 interrupt-controller; 240 #address-cells = <0>; 241 #interrupt-cells = <2>; 242 interrupts = <46 2>; 243 interrupt-parent = <&mpic>; 244 reg = <0x90c00 0x80>; 245 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 246 }; 247 248 serial0: serial@91a20 { 249 device_type = "serial"; 250 compatible = "fsl,mpc8560-scc-uart", 251 "fsl,cpm2-scc-uart"; 252 reg = <0x91a20 0x20 0x88100 0x100>; 253 fsl,cpm-brg = <2>; 254 fsl,cpm-command = <0x4a00000>; 255 interrupts = <41 8>; 256 interrupt-parent = <&cpmpic>; 257 }; 258 }; 259 }; 260 261 pci0: pci@fdf08000 { 262 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 263 interrupt-map = < 264 265 /* IDSEL 0x0c */ 266 0x6000 0 0 1 &mpic 1 1 267 0x6000 0 0 2 &mpic 2 1 268 0x6000 0 0 3 &mpic 3 1 269 0x6000 0 0 4 &mpic 4 1 270 271 /* IDSEL 0x0d */ 272 0x6800 0 0 1 &mpic 4 1 273 0x6800 0 0 2 &mpic 1 1 274 0x6800 0 0 3 &mpic 2 1 275 0x6800 0 0 4 &mpic 3 1 276 277 /* IDSEL 0x0e */ 278 0x7000 0 0 1 &mpic 3 1 279 0x7000 0 0 2 &mpic 4 1 280 0x7000 0 0 3 &mpic 1 1 281 0x7000 0 0 4 &mpic 2 1 282 283 /* IDSEL 0x0f */ 284 0x7800 0 0 1 &mpic 2 1 285 0x7800 0 0 2 &mpic 3 1 286 0x7800 0 0 3 &mpic 4 1 287 0x7800 0 0 4 &mpic 1 1>; 288 289 interrupt-parent = <&mpic>; 290 interrupts = <24 2>; 291 bus-range = <0 0>; 292 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 293 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 294 clock-frequency = <66666666>; 295 #interrupt-cells = <1>; 296 #size-cells = <2>; 297 #address-cells = <3>; 298 reg = <0xfdf08000 0x1000>; 299 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 300 device_type = "pci"; 301 }; 302}; 303