1/* 2 * Device Tree Source for Mosaix Technologies, Inc. ICON board 3 * 4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 model = "mosaixtech,icon"; 17 compatible = "mosaixtech,icon"; 18 dcr-parent = <&{/cpus/cpu@0}>; 19 20 aliases { 21 ethernet0 = &EMAC0; 22 serial0 = &UART0; 23 serial1 = &UART1; 24 serial2 = &UART2; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC,440SPe"; 34 reg = <0x00000000>; 35 clock-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */ 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; 39 i-cache-size = <32768>; 40 d-cache-size = <32768>; 41 dcr-controller; 42 dcr-access-method = "native"; 43 reset-type = <2>; /* Use chip-reset */ 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ 50 }; 51 52 UIC0: interrupt-controller0 { 53 compatible = "ibm,uic-440spe","ibm,uic"; 54 interrupt-controller; 55 cell-index = <0>; 56 dcr-reg = <0x0c0 0x009>; 57 #address-cells = <0>; 58 #size-cells = <0>; 59 #interrupt-cells = <2>; 60 }; 61 62 UIC1: interrupt-controller1 { 63 compatible = "ibm,uic-440spe","ibm,uic"; 64 interrupt-controller; 65 cell-index = <1>; 66 dcr-reg = <0x0d0 0x009>; 67 #address-cells = <0>; 68 #size-cells = <0>; 69 #interrupt-cells = <2>; 70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 71 interrupt-parent = <&UIC0>; 72 }; 73 74 UIC2: interrupt-controller2 { 75 compatible = "ibm,uic-440spe","ibm,uic"; 76 interrupt-controller; 77 cell-index = <2>; 78 dcr-reg = <0x0e0 0x009>; 79 #address-cells = <0>; 80 #size-cells = <0>; 81 #interrupt-cells = <2>; 82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 83 interrupt-parent = <&UIC0>; 84 }; 85 86 UIC3: interrupt-controller3 { 87 compatible = "ibm,uic-440spe","ibm,uic"; 88 interrupt-controller; 89 cell-index = <3>; 90 dcr-reg = <0x0f0 0x009>; 91 #address-cells = <0>; 92 #size-cells = <0>; 93 #interrupt-cells = <2>; 94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 95 interrupt-parent = <&UIC0>; 96 }; 97 98 SDR0: sdr { 99 compatible = "ibm,sdr-440spe"; 100 dcr-reg = <0x00e 0x002>; 101 }; 102 103 CPR0: cpr { 104 compatible = "ibm,cpr-440spe"; 105 dcr-reg = <0x00c 0x002>; 106 }; 107 108 MQ0: mq { 109 compatible = "ibm,mq-440spe"; 110 dcr-reg = <0x040 0x020>; 111 }; 112 113 plb { 114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; 115 #address-cells = <2>; 116 #size-cells = <1>; 117 /* addr-child addr-parent size */ 118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 119 0x4 0x00200000 0x4 0x00200000 0x00000400 120 0x4 0xe0000000 0x4 0xe0000000 0x20000000 121 0xc 0x00000000 0xc 0x00000000 0x20000000 122 0xd 0x00000000 0xd 0x00000000 0x80000000 123 0xd 0x80000000 0xd 0x80000000 0x80000000 124 0xe 0x00000000 0xe 0x00000000 0x80000000 125 0xe 0x80000000 0xe 0x80000000 0x80000000 126 0xf 0x00000000 0xf 0x00000000 0x80000000 127 0xf 0x80000000 0xf 0x80000000 0x80000000>; 128 clock-frequency = <0>; /* Filled in by U-Boot */ 129 130 SDRAM0: sdram { 131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; 132 dcr-reg = <0x010 0x002>; 133 }; 134 135 MAL0: mcmal { 136 compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; 137 dcr-reg = <0x180 0x062>; 138 num-tx-chans = <2>; 139 num-rx-chans = <1>; 140 interrupt-parent = <&MAL0>; 141 interrupts = <0x0 0x1 0x2 0x3 0x4>; 142 #interrupt-cells = <1>; 143 #address-cells = <0>; 144 #size-cells = <0>; 145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4 146 /*RXEOB*/ 0x1 &UIC1 0x7 0x4 147 /*SERR*/ 0x2 &UIC1 0x1 0x4 148 /*TXDE*/ 0x3 &UIC1 0x2 0x4 149 /*RXDE*/ 0x4 &UIC1 0x3 0x4>; 150 }; 151 152 POB0: opb { 153 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; 157 clock-frequency = <0>; /* Filled in by U-Boot */ 158 159 EBC0: ebc { 160 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; 161 dcr-reg = <0x012 0x002>; 162 #address-cells = <2>; 163 #size-cells = <1>; 164 clock-frequency = <0>; /* Filled in by U-Boot */ 165 /* ranges property is supplied by U-Boot */ 166 interrupts = <0x5 0x1>; 167 interrupt-parent = <&UIC1>; 168 169 nor_flash@0,0 { 170 compatible = "cfi-flash"; 171 bank-width = <2>; 172 reg = <0x00000000 0x00000000 0x01000000>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 partition@0 { 176 label = "kernel"; 177 reg = <0x00000000 0x001e0000>; 178 }; 179 partition@1e0000 { 180 label = "dtb"; 181 reg = <0x001e0000 0x00020000>; 182 }; 183 partition@200000 { 184 label = "root"; 185 reg = <0x00200000 0x00200000>; 186 }; 187 partition@400000 { 188 label = "user"; 189 reg = <0x00400000 0x00b60000>; 190 }; 191 partition@f60000 { 192 label = "env"; 193 reg = <0x00f60000 0x00040000>; 194 }; 195 partition@fa0000 { 196 label = "u-boot"; 197 reg = <0x00fa0000 0x00060000>; 198 }; 199 }; 200 }; 201 202 UART0: serial@f0000200 { 203 device_type = "serial"; 204 compatible = "ns16550"; 205 reg = <0xf0000200 0x00000008>; 206 virtual-reg = <0xa0000200>; 207 clock-frequency = <0>; /* Filled in by U-Boot */ 208 current-speed = <115200>; 209 interrupt-parent = <&UIC0>; 210 interrupts = <0x0 0x4>; 211 }; 212 213 UART1: serial@f0000300 { 214 device_type = "serial"; 215 compatible = "ns16550"; 216 reg = <0xf0000300 0x00000008>; 217 virtual-reg = <0xa0000300>; 218 clock-frequency = <0>; 219 current-speed = <0>; 220 interrupt-parent = <&UIC0>; 221 interrupts = <0x1 0x4>; 222 }; 223 224 225 UART2: serial@f0000600 { 226 device_type = "serial"; 227 compatible = "ns16550"; 228 reg = <0xf0000600 0x00000008>; 229 virtual-reg = <0xa0000600>; 230 clock-frequency = <0>; 231 current-speed = <0>; 232 interrupt-parent = <&UIC1>; 233 interrupts = <0x5 0x4>; 234 }; 235 236 IIC0: i2c@f0000400 { 237 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 238 reg = <0xf0000400 0x00000014>; 239 interrupt-parent = <&UIC0>; 240 interrupts = <0x2 0x4>; 241 }; 242 243 IIC1: i2c@f0000500 { 244 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 245 reg = <0xf0000500 0x00000014>; 246 interrupt-parent = <&UIC0>; 247 interrupts = <0x3 0x4>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 rtc@68 { 252 compatible = "st,m41t00"; 253 reg = <0x68>; 254 }; 255 }; 256 257 EMAC0: ethernet@f0000800 { 258 linux,network-index = <0x0>; 259 device_type = "network"; 260 compatible = "ibm,emac-440spe", "ibm,emac4"; 261 interrupt-parent = <&UIC1>; 262 interrupts = <0x1c 0x4 0x1d 0x4>; 263 reg = <0xf0000800 0x00000074>; 264 local-mac-address = [000000000000]; 265 mal-device = <&MAL0>; 266 mal-tx-channel = <0>; 267 mal-rx-channel = <0>; 268 cell-index = <0>; 269 max-frame-size = <9000>; 270 rx-fifo-size = <4096>; 271 tx-fifo-size = <2048>; 272 phy-mode = "gmii"; 273 phy-map = <0x00000000>; 274 has-inverted-stacr-oc; 275 has-new-stacr-staopc; 276 }; 277 }; 278 279 PCIX0: pci@c0ec00000 { 280 device_type = "pci"; 281 #interrupt-cells = <1>; 282 #size-cells = <2>; 283 #address-cells = <3>; 284 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; 285 primary; 286 large-inbound-windows; 287 enable-msi-hole; 288 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 289 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 290 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 291 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 292 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 293 294 /* Outbound ranges, one memory and one IO, 295 * later cannot be changed 296 */ 297 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 298 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 299 300 /* Inbound 4GB range starting at 0 */ 301 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 302 303 /* This drives busses 0 to 0xf */ 304 bus-range = <0x0 0xf>; 305 306 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */ 307 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 308 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>; 309 }; 310 311 PCIE0: pcie@d00000000 { 312 device_type = "pci"; 313 #interrupt-cells = <1>; 314 #size-cells = <2>; 315 #address-cells = <3>; 316 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 317 primary; 318 port = <0x0>; /* port number */ 319 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 320 0x0000000c 0x10000000 0x00001000>; /* Registers */ 321 dcr-reg = <0x100 0x020>; 322 sdr-base = <0x300>; 323 324 /* Outbound ranges, one memory and one IO, 325 * later cannot be changed 326 */ 327 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 328 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 329 330 /* Inbound 4GB range starting at 0 */ 331 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 332 333 /* This drives busses 0x10 to 0x1f */ 334 bus-range = <0x10 0x1f>; 335 336 /* Legacy interrupts (note the weird polarity, the bridge seems 337 * to invert PCIe legacy interrupts). 338 * We are de-swizzling here because the numbers are actually for 339 * port of the root complex virtual P2P bridge. But I want 340 * to avoid putting a node for it in the tree, so the numbers 341 * below are basically de-swizzled numbers. 342 * The real slot is on idsel 0, so the swizzling is 1:1 343 */ 344 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 345 interrupt-map = < 346 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ 347 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ 348 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ 349 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; 350 }; 351 352 PCIE1: pcie@d20000000 { 353 device_type = "pci"; 354 #interrupt-cells = <1>; 355 #size-cells = <2>; 356 #address-cells = <3>; 357 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 358 primary; 359 port = <0x1>; /* port number */ 360 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 361 0x0000000c 0x10001000 0x00001000>; /* Registers */ 362 dcr-reg = <0x120 0x020>; 363 sdr-base = <0x340>; 364 365 /* Outbound ranges, one memory and one IO, 366 * later cannot be changed 367 */ 368 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 369 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 370 371 /* Inbound 4GB range starting at 0 */ 372 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 373 374 /* This drives busses 0x20 to 0x2f */ 375 bus-range = <0x20 0x2f>; 376 377 /* Legacy interrupts (note the weird polarity, the bridge seems 378 * to invert PCIe legacy interrupts). 379 * We are de-swizzling here because the numbers are actually for 380 * port of the root complex virtual P2P bridge. But I want 381 * to avoid putting a node for it in the tree, so the numbers 382 * below are basically de-swizzled numbers. 383 * The real slot is on idsel 0, so the swizzling is 1:1 384 */ 385 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 386 interrupt-map = < 387 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ 388 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ 389 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ 390 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; 391 }; 392 393 I2O: i2o@400100000 { 394 compatible = "ibm,i2o-440spe"; 395 reg = <0x00000004 0x00100000 0x100>; 396 dcr-reg = <0x060 0x020>; 397 }; 398 399 DMA0: dma0@400100100 { 400 compatible = "ibm,dma-440spe"; 401 cell-index = <0>; 402 reg = <0x00000004 0x00100100 0x100>; 403 dcr-reg = <0x060 0x020>; 404 interrupt-parent = <&DMA0>; 405 interrupts = <0 1>; 406 #interrupt-cells = <1>; 407 #address-cells = <0>; 408 #size-cells = <0>; 409 interrupt-map = < 410 0 &UIC0 0x14 4 411 1 &UIC1 0x16 4>; 412 }; 413 414 DMA1: dma1@400100200 { 415 compatible = "ibm,dma-440spe"; 416 cell-index = <1>; 417 reg = <0x00000004 0x00100200 0x100>; 418 dcr-reg = <0x060 0x020>; 419 interrupt-parent = <&DMA1>; 420 interrupts = <0 1>; 421 #interrupt-cells = <1>; 422 #address-cells = <0>; 423 #size-cells = <0>; 424 interrupt-map = < 425 0 &UIC0 0x16 4 426 1 &UIC1 0x16 4>; 427 }; 428 429 xor-accel@400200000 { 430 compatible = "amcc,xor-accelerator"; 431 reg = <0x00000004 0x00200000 0x400>; 432 interrupt-parent = <&UIC1>; 433 interrupts = <0x1f 4>; 434 }; 435 }; 436 437 chosen { 438 stdout-path = "/plb/opb/serial@f0000200"; 439 }; 440}; 441