1/* 2 * T4240RDB Device Tree Source 3 * 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "t4240si-pre.dtsi" 36 37/ { 38 model = "fsl,T4240RDB"; 39 compatible = "fsl,T4240RDB"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 sgmii_phy21 = &sgmiiphy21; 46 sgmii_phy22 = &sgmiiphy22; 47 sgmii_phy23 = &sgmiiphy23; 48 sgmii_phy24 = &sgmiiphy24; 49 sgmii_phy41 = &sgmiiphy41; 50 sgmii_phy42 = &sgmiiphy42; 51 sgmii_phy43 = &sgmiiphy43; 52 sgmii_phy44 = &sgmiiphy44; 53 }; 54 55 ifc: localbus@ffe124000 { 56 reg = <0xf 0xfe124000 0 0x2000>; 57 ranges = <0 0 0xf 0xe8000000 0x08000000 58 2 0 0xf 0xff800000 0x00010000 59 3 0 0xf 0xffdf0000 0x00008000>; 60 61 nor@0,0 { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "cfi-flash"; 65 reg = <0x0 0x0 0x8000000>; 66 67 bank-width = <2>; 68 device-width = <1>; 69 }; 70 71 nand@2,0 { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 compatible = "fsl,ifc-nand"; 75 reg = <0x2 0x0 0x10000>; 76 }; 77 }; 78 79 memory { 80 device_type = "memory"; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 bman_fbpr: bman-fbpr { 89 size = <0 0x1000000>; 90 alignment = <0 0x1000000>; 91 }; 92 qman_fqd: qman-fqd { 93 size = <0 0x400000>; 94 alignment = <0 0x400000>; 95 }; 96 qman_pfdr: qman-pfdr { 97 size = <0 0x2000000>; 98 alignment = <0 0x2000000>; 99 }; 100 }; 101 102 dcsr: dcsr@f00000000 { 103 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 104 }; 105 106 bportals: bman-portals@ff4000000 { 107 ranges = <0x0 0xf 0xf4000000 0x2000000>; 108 }; 109 110 qportals: qman-portals@ff6000000 { 111 ranges = <0x0 0xf 0xf6000000 0x2000000>; 112 }; 113 114 soc: soc@ffe000000 { 115 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 116 reg = <0xf 0xfe000000 0 0x00001000>; 117 spi@110000 { 118 flash@0 { 119 #address-cells = <1>; 120 #size-cells = <1>; 121 compatible = "sst,sst25wf040", "jedec,spi-nor"; 122 reg = <0>; 123 spi-max-frequency = <40000000>; /* input clock */ 124 }; 125 }; 126 127 i2c@118000 { 128 hwmon@2f { 129 compatible = "winbond,w83793"; 130 reg = <0x2f>; 131 }; 132 eeprom@52 { 133 compatible = "atmel,24c256"; 134 reg = <0x52>; 135 }; 136 eeprom@54 { 137 compatible = "atmel,24c256"; 138 reg = <0x54>; 139 }; 140 eeprom@56 { 141 compatible = "atmel,24c256"; 142 reg = <0x56>; 143 }; 144 rtc@68 { 145 compatible = "dallas,ds1374"; 146 reg = <0x68>; 147 }; 148 }; 149 150 sdhc@114000 { 151 voltage-ranges = <1800 1800 3300 3300>; 152 }; 153 154 fman@400000 { 155 ethernet@e0000 { 156 phy-handle = <&sgmiiphy21>; 157 phy-connection-type = "sgmii"; 158 }; 159 160 ethernet@e2000 { 161 phy-handle = <&sgmiiphy22>; 162 phy-connection-type = "sgmii"; 163 }; 164 165 ethernet@e4000 { 166 phy-handle = <&sgmiiphy23>; 167 phy-connection-type = "sgmii"; 168 }; 169 170 ethernet@e6000 { 171 phy-handle = <&sgmiiphy24>; 172 phy-connection-type = "sgmii"; 173 }; 174 175 ethernet@e8000 { 176 status = "disabled"; 177 }; 178 179 ethernet@ea000 { 180 status = "disabled"; 181 }; 182 183 ethernet@f0000 { 184 phy-handle = <&xfiphy1>; 185 phy-connection-type = "xgmii"; 186 }; 187 188 ethernet@f2000 { 189 phy-handle = <&xfiphy2>; 190 phy-connection-type = "xgmii"; 191 }; 192 }; 193 194 fman@500000 { 195 ethernet@e0000 { 196 phy-handle = <&sgmiiphy41>; 197 phy-connection-type = "sgmii"; 198 }; 199 200 ethernet@e2000 { 201 phy-handle = <&sgmiiphy42>; 202 phy-connection-type = "sgmii"; 203 }; 204 205 ethernet@e4000 { 206 phy-handle = <&sgmiiphy43>; 207 phy-connection-type = "sgmii"; 208 }; 209 210 ethernet@e6000 { 211 phy-handle = <&sgmiiphy44>; 212 phy-connection-type = "sgmii"; 213 }; 214 215 ethernet@e8000 { 216 status = "disabled"; 217 }; 218 219 ethernet@ea000 { 220 status = "disabled"; 221 }; 222 223 ethernet@f0000 { 224 phy-handle = <&xfiphy3>; 225 phy-connection-type = "xgmii"; 226 }; 227 228 ethernet@f2000 { 229 phy-handle = <&xfiphy4>; 230 phy-connection-type = "xgmii"; 231 }; 232 233 mdio@fc000 { 234 sgmiiphy21: ethernet-phy@0 { 235 reg = <0x0>; 236 }; 237 238 sgmiiphy22: ethernet-phy@1 { 239 reg = <0x1>; 240 }; 241 242 sgmiiphy23: ethernet-phy@2 { 243 reg = <0x2>; 244 }; 245 246 sgmiiphy24: ethernet-phy@3 { 247 reg = <0x3>; 248 }; 249 250 sgmiiphy41: ethernet-phy@4 { 251 reg = <0x4>; 252 }; 253 254 sgmiiphy42: ethernet-phy@5 { 255 reg = <0x5>; 256 }; 257 258 sgmiiphy43: ethernet-phy@6 { 259 reg = <0x6>; 260 }; 261 262 sgmiiphy44: ethernet-phy@7 { 263 reg = <0x7>; 264 }; 265 }; 266 267 mdio@fd000 { 268 xfiphy1: ethernet-phy@10 { 269 compatible = "ethernet-phy-id13e5.1002"; 270 reg = <0x10>; 271 }; 272 273 xfiphy2: ethernet-phy@11 { 274 compatible = "ethernet-phy-id13e5.1002"; 275 reg = <0x11>; 276 }; 277 278 xfiphy3: ethernet-phy@13 { 279 compatible = "ethernet-phy-id13e5.1002"; 280 reg = <0x13>; 281 }; 282 283 xfiphy4: ethernet-phy@12 { 284 compatible = "ethernet-phy-id13e5.1002"; 285 reg = <0x12>; 286 }; 287 }; 288 }; 289 }; 290 291 pci0: pcie@ffe240000 { 292 reg = <0xf 0xfe240000 0 0x10000>; 293 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 294 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 295 pcie@0 { 296 ranges = <0x02000000 0 0xe0000000 297 0x02000000 0 0xe0000000 298 0 0x20000000 299 300 0x01000000 0 0x00000000 301 0x01000000 0 0x00000000 302 0 0x00010000>; 303 }; 304 }; 305 306 pci1: pcie@ffe250000 { 307 reg = <0xf 0xfe250000 0 0x10000>; 308 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 309 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 310 pcie@0 { 311 ranges = <0x02000000 0 0xe0000000 312 0x02000000 0 0xe0000000 313 0 0x20000000 314 315 0x01000000 0 0x00000000 316 0x01000000 0 0x00000000 317 0 0x00010000>; 318 }; 319 }; 320 321 pci2: pcie@ffe260000 { 322 reg = <0xf 0xfe260000 0 0x1000>; 323 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 324 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 325 pcie@0 { 326 ranges = <0x02000000 0 0xe0000000 327 0x02000000 0 0xe0000000 328 0 0x20000000 329 330 0x01000000 0 0x00000000 331 0x01000000 0 0x00000000 332 0 0x00010000>; 333 }; 334 }; 335 336 pci3: pcie@ffe270000 { 337 reg = <0xf 0xfe270000 0 0x10000>; 338 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 339 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 340 pcie@0 { 341 ranges = <0x02000000 0 0xe0000000 342 0x02000000 0 0xe0000000 343 0 0x20000000 344 345 0x01000000 0 0x00000000 346 0x01000000 0 0x00000000 347 0 0x00010000>; 348 }; 349 }; 350 351 rio: rapidio@ffe0c0000 { 352 reg = <0xf 0xfe0c0000 0 0x11000>; 353 354 port1 { 355 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 356 }; 357 port2 { 358 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 359 }; 360 }; 361}; 362 363/include/ "t4240si-post.dtsi" 364