1/* 2 * T4240QDS Device Tree Source 3 * 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "t4240si-pre.dtsi" 36 37/ { 38 model = "fsl,T4240QDS"; 39 compatible = "fsl,T4240QDS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases{ 45 phy_rgmii1 = &phyrgmii1; 46 phy_rgmii2 = &phyrgmii2; 47 phy_sgmii3 = &phy3; 48 phy_sgmii4 = &phy4; 49 phy_sgmii11 = &phy11; 50 phy_sgmii12 = &phy12; 51 sgmii_phy11 = &sgmiiphy11; 52 sgmii_phy12 = &sgmiiphy12; 53 sgmii_phy13 = &sgmiiphy13; 54 sgmii_phy14 = &sgmiiphy14; 55 sgmii_phy21 = &sgmiiphy21; 56 sgmii_phy22 = &sgmiiphy22; 57 sgmii_phy23 = &sgmiiphy23; 58 sgmii_phy24 = &sgmiiphy24; 59 sgmii_phy31 = &sgmiiphy31; 60 sgmii_phy32 = &sgmiiphy32; 61 sgmii_phy33 = &sgmiiphy33; 62 sgmii_phy34 = &sgmiiphy34; 63 sgmii_phy41 = &sgmiiphy41; 64 sgmii_phy42 = &sgmiiphy42; 65 sgmii_phy43 = &sgmiiphy43; 66 sgmii_phy44 = &sgmiiphy44; 67 phy_xfi1 = &xfiphy1; 68 phy_xfi2 = &xfiphy2; 69 phy_xfi3 = &xfiphy3; 70 phy_xfi4 = &xfiphy4; 71 xfi_pcs_mdio1 = &xfimdio0; 72 xfi_pcs_mdio2 = &xfimdio1; 73 xfi_pcs_mdio3 = &xfimdio2; 74 xfi_pcs_mdio4 = &xfimdio3; 75 emi1_rgmii = &t4240mdio0; 76 emi1_slot1 = &t4240mdio1; 77 emi1_slot2 = &t4240mdio2; 78 emi1_slot3 = &t4240mdio3; 79 emi1_slot4 = &t4240mdio4; 80 }; 81 82 ifc: localbus@ffe124000 { 83 reg = <0xf 0xfe124000 0 0x2000>; 84 ranges = <0 0 0xf 0xe8000000 0x08000000 85 2 0 0xf 0xff800000 0x00010000 86 3 0 0xf 0xffdf0000 0x00008000>; 87 88 nor@0,0 { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "cfi-flash"; 92 reg = <0x0 0x0 0x8000000>; 93 94 bank-width = <2>; 95 device-width = <1>; 96 }; 97 98 nand@2,0 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,ifc-nand"; 102 reg = <0x2 0x0 0x10000>; 103 104 partition@0 { 105 /* This location must not be altered */ 106 /* 1MB for u-boot Bootloader Image */ 107 reg = <0x0 0x00100000>; 108 label = "NAND U-Boot Image"; 109 read-only; 110 }; 111 112 partition@100000 { 113 /* 1MB for DTB Image */ 114 reg = <0x00100000 0x00100000>; 115 label = "NAND DTB Image"; 116 }; 117 118 partition@200000 { 119 /* 10MB for Linux Kernel Image */ 120 reg = <0x00200000 0x00A00000>; 121 label = "NAND Linux Kernel Image"; 122 }; 123 124 partition@C00000 { 125 /* 500MB for Root file System Image */ 126 reg = <0x00c00000 0x1F400000>; 127 label = "NAND RFS Image"; 128 }; 129 }; 130 131 board-control@3,0 { 132 #address-cells = <1>; 133 #size-cells = <1>; 134 compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis"; 135 reg = <3 0 0x300>; 136 ranges = <0 3 0 0x300>; 137 138 mdio-mux-emi1 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 compatible = "mdio-mux-mmioreg", "mdio-mux"; 142 mdio-parent-bus = <&mdio1>; 143 reg = <0x54 1>; 144 mux-mask = <0xe0>; 145 146 t4240mdio0: mdio@0 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <0>; 150 151 phyrgmii1: ethernet-phy@1 { 152 reg = <0x1>; 153 }; 154 155 phyrgmii2: ethernet-phy@2 { 156 reg = <0x2>; 157 }; 158 }; 159 160 t4240mdio1: mdio@20 { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 reg = <0x20>; 164 status = "disabled"; 165 166 phy1: ethernet-phy@0 { 167 reg = <0x0>; 168 }; 169 170 phy2: ethernet-phy@1 { 171 reg = <0x1>; 172 }; 173 174 phy3: ethernet-phy@2 { 175 reg = <0x2>; 176 }; 177 178 phy4: ethernet-phy@3 { 179 reg = <0x3>; 180 }; 181 182 sgmiiphy11: ethernet-phy@1c { 183 reg = <0x1c>; 184 }; 185 186 sgmiiphy12: ethernet-phy@1d { 187 reg = <0x1d>; 188 }; 189 190 sgmiiphy13: ethernet-phy@1e { 191 reg = <0x1e>; 192 }; 193 194 sgmiiphy14: ethernet-phy@1f { 195 reg = <0x1f>; 196 }; 197 }; 198 199 t4240mdio2: mdio@40 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 reg = <0x40>; 203 status = "disabled"; 204 205 phy5: ethernet-phy@4 { 206 reg = <0x4>; 207 }; 208 209 phy6: ethernet-phy@5 { 210 reg = <0x5>; 211 }; 212 213 phy7: ethernet-phy@6 { 214 reg = <0x6>; 215 }; 216 217 phy8: ethernet-phy@7 { 218 reg = <0x7>; 219 }; 220 221 sgmiiphy21: ethernet-phy@1c { 222 reg = <0x1c>; 223 }; 224 225 sgmiiphy22: ethernet-phy@1d { 226 reg = <0x1d>; 227 }; 228 229 sgmiiphy23: ethernet-phy@1e { 230 reg = <0x1e>; 231 }; 232 233 sgmiiphy24: ethernet-phy@1f { 234 reg = <0x1f>; 235 }; 236 }; 237 238 t4240mdio3: mdio@60 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x60>; 242 status = "disabled"; 243 244 phy9: ethernet-phy@8 { 245 reg = <0x8>; 246 }; 247 248 phy10: ethernet-phy@9 { 249 reg = <0x9>; 250 }; 251 252 phy11: ethernet-phy@a { 253 reg = <0xa>; 254 }; 255 256 phy12: ethernet-phy@b { 257 reg = <0xb>; 258 }; 259 260 sgmiiphy31: ethernet-phy@1c { 261 reg = <0x1c>; 262 }; 263 264 sgmiiphy32: ethernet-phy@1d { 265 reg = <0x1d>; 266 }; 267 268 sgmiiphy33: ethernet-phy@1e { 269 reg = <0x1e>; 270 }; 271 272 sgmiiphy34: ethernet-phy@1f { 273 reg = <0x1f>; 274 }; 275 }; 276 277 t4240mdio4: mdio@80 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x80>; 281 status = "disabled"; 282 283 phy13: ethernet-phy@c { 284 reg = <0xc>; 285 }; 286 287 phy14: ethernet-phy@d { 288 reg = <0xd>; 289 }; 290 291 phy15: ethernet-phy@e { 292 reg = <0xe>; 293 }; 294 295 phy16: ethernet-phy@f { 296 reg = <0xf>; 297 }; 298 299 sgmiiphy41: ethernet-phy@1c { 300 reg = <0x1c>; 301 }; 302 303 sgmiiphy42: ethernet-phy@1d { 304 reg = <0x1d>; 305 }; 306 307 sgmiiphy43: ethernet-phy@1e { 308 reg = <0x1e>; 309 }; 310 311 sgmiiphy44: ethernet-phy@1f { 312 reg = <0x1f>; 313 }; 314 }; 315 }; 316 }; 317 }; 318 319 memory { 320 device_type = "memory"; 321 }; 322 323 reserved-memory { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 ranges; 327 328 bman_fbpr: bman-fbpr { 329 size = <0 0x1000000>; 330 alignment = <0 0x1000000>; 331 }; 332 qman_fqd: qman-fqd { 333 size = <0 0x400000>; 334 alignment = <0 0x400000>; 335 }; 336 qman_pfdr: qman-pfdr { 337 size = <0 0x2000000>; 338 alignment = <0 0x2000000>; 339 }; 340 }; 341 342 dcsr: dcsr@f00000000 { 343 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 344 }; 345 346 bportals: bman-portals@ff4000000 { 347 ranges = <0x0 0xf 0xf4000000 0x2000000>; 348 }; 349 350 qportals: qman-portals@ff6000000 { 351 ranges = <0x0 0xf 0xf6000000 0x2000000>; 352 }; 353 354 soc: soc@ffe000000 { 355 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 356 reg = <0xf 0xfe000000 0 0x00001000>; 357 spi@110000 { 358 flash@0 { 359 #address-cells = <1>; 360 #size-cells = <1>; 361 compatible = "sst,sst25wf040", "jedec,spi-nor"; 362 reg = <0>; 363 spi-max-frequency = <40000000>; /* input clock */ 364 }; 365 }; 366 367 i2c@118000 { 368 mux@77 { 369 compatible = "nxp,pca9547"; 370 reg = <0x77>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 i2c@0 { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <0>; 378 379 eeprom@51 { 380 compatible = "atmel,24c256"; 381 reg = <0x51>; 382 }; 383 eeprom@52 { 384 compatible = "atmel,24c256"; 385 reg = <0x52>; 386 }; 387 eeprom@53 { 388 compatible = "atmel,24c256"; 389 reg = <0x53>; 390 }; 391 eeprom@54 { 392 compatible = "atmel,24c256"; 393 reg = <0x54>; 394 }; 395 eeprom@55 { 396 compatible = "atmel,24c256"; 397 reg = <0x55>; 398 }; 399 eeprom@56 { 400 compatible = "atmel,24c256"; 401 reg = <0x56>; 402 }; 403 rtc@68 { 404 compatible = "dallas,ds3232"; 405 reg = <0x68>; 406 interrupts = <0x1 0x1 0 0>; 407 }; 408 }; 409 410 i2c@2 { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0x2>; 414 415 ina220@40 { 416 compatible = "ti,ina220"; 417 reg = <0x40>; 418 shunt-resistor = <1000>; 419 }; 420 421 ina220@41 { 422 compatible = "ti,ina220"; 423 reg = <0x41>; 424 shunt-resistor = <1000>; 425 }; 426 427 ina220@44 { 428 compatible = "ti,ina220"; 429 reg = <0x44>; 430 shunt-resistor = <1000>; 431 }; 432 433 ina220@45 { 434 compatible = "ti,ina220"; 435 reg = <0x45>; 436 shunt-resistor = <1000>; 437 }; 438 439 ina220@46 { 440 compatible = "ti,ina220"; 441 reg = <0x46>; 442 shunt-resistor = <1000>; 443 }; 444 445 ina220@47 { 446 compatible = "ti,ina220"; 447 reg = <0x47>; 448 shunt-resistor = <1000>; 449 }; 450 }; 451 }; 452 }; 453 454 sdhc@114000 { 455 voltage-ranges = <1800 1800 3300 3300>; 456 }; 457 458 fman@400000 { 459 port@83000 { 460 status = "disabled"; 461 }; 462 463 port@84000 { 464 status = "disabled"; 465 }; 466 467 port@85000 { 468 status = "disabled"; 469 }; 470 471 port@86000 { 472 status = "disabled"; 473 }; 474 475 port@87000 { 476 status = "disabled"; 477 }; 478 479 ethernet@e0000 { 480 phy-handle = <&phy5>; 481 phy-connection-type = "sgmii"; 482 }; 483 484 ethernet@e2000 { 485 phy-handle = <&phy6>; 486 phy-connection-type = "sgmii"; 487 }; 488 489 ethernet@e4000 { 490 phy-handle = <&phy7>; 491 phy-connection-type = "sgmii"; 492 }; 493 494 ethernet@e6000 { 495 phy-handle = <&phy8>; 496 phy-connection-type = "sgmii"; 497 }; 498 499 ethernet@e8000 { 500 phy-handle = <&phyrgmii2>; 501 phy-connection-type = "rgmii"; 502 }; 503 504 ethernet@ea000 { 505 phy-handle = <&phy2>; 506 phy-connection-type = "sgmii"; 507 }; 508 509 ethernet@f0000 { 510 phy-handle = <&xauiphy1>; 511 phy-connection-type = "xgmii"; 512 }; 513 514 ethernet@f2000 { 515 phy-handle = <&xauiphy2>; 516 phy-connection-type = "xgmii"; 517 }; 518 519 xfimdio0: mdio@f1000 { 520 status = "disabled"; 521 522 xfiphy1: ethernet-phy@0 { 523 compatible = "ethernet-phy-ieee802.3-c45"; 524 reg = <0x0>; 525 }; 526 }; 527 528 xfimdio1: mdio@f3000 { 529 status = "disabled"; 530 531 xfiphy2: ethernet-phy@0 { 532 compatible = "ethernet-phy-ieee802.3-c45"; 533 reg = <0x0>; 534 }; 535 }; 536 }; 537 538 fman@500000 { 539 port@84000 { 540 status = "disabled"; 541 }; 542 543 port@85000 { 544 status = "disabled"; 545 }; 546 547 port@86000 { 548 status = "disabled"; 549 }; 550 551 port@87000 { 552 status = "disabled"; 553 }; 554 555 ethernet@e0000 { 556 phy-handle = <&phy13>; 557 phy-connection-type = "sgmii"; 558 }; 559 560 ethernet@e2000 { 561 phy-handle = <&phy14>; 562 phy-connection-type = "sgmii"; 563 }; 564 565 ethernet@e4000 { 566 phy-handle = <&phy15>; 567 phy-connection-type = "sgmii"; 568 }; 569 570 ethernet@e6000 { 571 phy-handle = <&phy16>; 572 phy-connection-type = "sgmii"; 573 }; 574 575 ethernet@e8000 { 576 phy-handle = <&phyrgmii1>; 577 phy-connection-type = "rgmii"; 578 }; 579 580 ethernet@ea000 { 581 phy-handle = <&phy10>; 582 phy-connection-type = "sgmii"; 583 }; 584 585 ethernet@f0000 { 586 phy-handle = <&xauiphy3>; 587 phy-connection-type = "xgmii"; 588 }; 589 590 ethernet@f2000 { 591 phy-handle = <&xauiphy4>; 592 phy-connection-type = "xgmii"; 593 }; 594 595 xfimdio2: mdio@f1000 { 596 status = "disabled"; 597 598 xfiphy3: ethernet-phy@0 { 599 compatible = "ethernet-phy-ieee802.3-c45"; 600 reg = <0x0>; 601 }; 602 }; 603 604 xfimdio3: mdio@f3000 { 605 status = "disabled"; 606 607 xfiphy4: ethernet-phy@0 { 608 compatible = "ethernet-phy-ieee802.3-c45"; 609 reg = <0x0>; 610 }; 611 }; 612 613 mdio@fd000 { 614 xauiphy1: ethernet-phy@0 { 615 compatible = "ethernet-phy-ieee802.3-c45"; 616 reg = <0x0>; 617 }; 618 619 xauiphy2: ethernet-phy@1 { 620 compatible = "ethernet-phy-ieee802.3-c45"; 621 reg = <0x1>; 622 }; 623 624 xauiphy3: ethernet-phy@2 { 625 compatible = "ethernet-phy-ieee802.3-c45"; 626 reg = <0x2>; 627 }; 628 629 xauiphy4: ethernet-phy@3 { 630 compatible = "ethernet-phy-ieee802.3-c45"; 631 reg = <0x3>; 632 }; 633 }; 634 }; 635 }; 636 637 pci0: pcie@ffe240000 { 638 reg = <0xf 0xfe240000 0 0x10000>; 639 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 640 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 641 pcie@0 { 642 ranges = <0x02000000 0 0xe0000000 643 0x02000000 0 0xe0000000 644 0 0x20000000 645 646 0x01000000 0 0x00000000 647 0x01000000 0 0x00000000 648 0 0x00010000>; 649 }; 650 }; 651 652 pci1: pcie@ffe250000 { 653 reg = <0xf 0xfe250000 0 0x10000>; 654 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 655 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 656 pcie@0 { 657 ranges = <0x02000000 0 0xe0000000 658 0x02000000 0 0xe0000000 659 0 0x20000000 660 661 0x01000000 0 0x00000000 662 0x01000000 0 0x00000000 663 0 0x00010000>; 664 }; 665 }; 666 667 pci2: pcie@ffe260000 { 668 reg = <0xf 0xfe260000 0 0x1000>; 669 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 670 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 671 pcie@0 { 672 ranges = <0x02000000 0 0xe0000000 673 0x02000000 0 0xe0000000 674 0 0x20000000 675 676 0x01000000 0 0x00000000 677 0x01000000 0 0x00000000 678 0 0x00010000>; 679 }; 680 }; 681 682 pci3: pcie@ffe270000 { 683 reg = <0xf 0xfe270000 0 0x10000>; 684 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 685 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 686 pcie@0 { 687 ranges = <0x02000000 0 0xe0000000 688 0x02000000 0 0xe0000000 689 0 0x20000000 690 691 0x01000000 0 0x00000000 692 0x01000000 0 0x00000000 693 0 0x00010000>; 694 }; 695 }; 696 rio: rapidio@ffe0c0000 { 697 reg = <0xf 0xfe0c0000 0 0x11000>; 698 699 port1 { 700 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 701 }; 702 port2 { 703 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 704 }; 705 }; 706}; 707 708/include/ "t4240si-post.dtsi" 709