1/* 2 * T1040RDB/T1042RDB Device Tree Source 3 * 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/ { 36 aliases { 37 phy_rgmii_0 = &phy_rgmii_0; 38 phy_rgmii_1 = &phy_rgmii_1; 39 phy_sgmii_2 = &phy_sgmii_2; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 bman_fbpr: bman-fbpr { 48 size = <0 0x1000000>; 49 alignment = <0 0x1000000>; 50 }; 51 qman_fqd: qman-fqd { 52 size = <0 0x400000>; 53 alignment = <0 0x400000>; 54 }; 55 qman_pfdr: qman-pfdr { 56 size = <0 0x2000000>; 57 alignment = <0 0x2000000>; 58 }; 59 }; 60 61 ifc: localbus@ffe124000 { 62 reg = <0xf 0xfe124000 0 0x2000>; 63 ranges = <0 0 0xf 0xe8000000 0x08000000 64 2 0 0xf 0xff800000 0x00010000 65 3 0 0xf 0xffdf0000 0x00008000>; 66 67 nor@0,0 { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 compatible = "cfi-flash"; 71 reg = <0x0 0x0 0x8000000>; 72 bank-width = <2>; 73 device-width = <1>; 74 }; 75 76 nand@2,0 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "fsl,ifc-nand"; 80 reg = <0x2 0x0 0x10000>; 81 }; 82 83 cpld@3,0 { 84 reg = <3 0 0x300>; 85 }; 86 }; 87 88 memory { 89 device_type = "memory"; 90 }; 91 92 dcsr: dcsr@f00000000 { 93 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 94 }; 95 96 bportals: bman-portals@ff4000000 { 97 ranges = <0x0 0xf 0xf4000000 0x2000000>; 98 }; 99 100 qportals: qman-portals@ff6000000 { 101 ranges = <0x0 0xf 0xf6000000 0x2000000>; 102 }; 103 104 soc: soc@ffe000000 { 105 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 106 reg = <0xf 0xfe000000 0 0x00001000>; 107 108 spi@110000 { 109 flash@0 { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 compatible = "micron,n25q512ax3", "jedec,spi-nor"; 113 reg = <0>; 114 spi-max-frequency = <10000000>; /* input clock */ 115 }; 116 slic@3 { 117 compatible = "maxim,ds26522"; 118 reg = <3>; 119 spi-max-frequency = <2000000>; /* input clock */ 120 }; 121 }; 122 123 i2c@118000 { 124 adt7461@4c { 125 compatible = "adi,adt7461"; 126 reg = <0x4c>; 127 }; 128 }; 129 130 i2c@118100 { 131 pca9546@77 { 132 compatible = "nxp,pca9546"; 133 reg = <0x77>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 fman@400000 { 140 ethernet@e6000 { 141 phy-handle = <&phy_rgmii_0>; 142 phy-connection-type = "rgmii-id"; 143 }; 144 145 ethernet@e8000 { 146 phy-handle = <&phy_rgmii_1>; 147 phy-connection-type = "rgmii-id"; 148 }; 149 150 mdio0: mdio@fc000 { 151 phy_sgmii_2: ethernet-phy@3 { 152 reg = <0x03>; 153 }; 154 155 phy_rgmii_0: ethernet-phy@1 { 156 reg = <0x01>; 157 }; 158 159 phy_rgmii_1: ethernet-phy@2 { 160 reg = <0x02>; 161 }; 162 }; 163 }; 164 }; 165 166 pci0: pcie@ffe240000 { 167 reg = <0xf 0xfe240000 0 0x10000>; 168 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 169 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 170 pcie@0 { 171 ranges = <0x02000000 0 0xe0000000 172 0x02000000 0 0xe0000000 173 0 0x10000000 174 175 0x01000000 0 0x00000000 176 0x01000000 0 0x00000000 177 0 0x00010000>; 178 }; 179 }; 180 181 pci1: pcie@ffe250000 { 182 reg = <0xf 0xfe250000 0 0x10000>; 183 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 184 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 185 pcie@0 { 186 ranges = <0x02000000 0 0xe0000000 187 0x02000000 0 0xe0000000 188 0 0x10000000 189 190 0x01000000 0 0x00000000 191 0x01000000 0 0x00000000 192 0 0x00010000>; 193 }; 194 }; 195 196 pci2: pcie@ffe260000 { 197 reg = <0xf 0xfe260000 0 0x10000>; 198 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 199 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 200 pcie@0 { 201 ranges = <0x02000000 0 0xe0000000 202 0x02000000 0 0xe0000000 203 0 0x10000000 204 205 0x01000000 0 0x00000000 206 0x01000000 0 0x00000000 207 0 0x00010000>; 208 }; 209 }; 210 211 pci3: pcie@ffe270000 { 212 reg = <0xf 0xfe270000 0 0x10000>; 213 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 214 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 215 pcie@0 { 216 ranges = <0x02000000 0 0xe0000000 217 0x02000000 0 0xe0000000 218 0 0x10000000 219 220 0x01000000 0 0x00000000 221 0x01000000 0 0x00000000 222 0 0x00010000>; 223 }; 224 }; 225 226 qe: qe@ffe140000 { 227 ranges = <0x0 0xf 0xfe140000 0x40000>; 228 reg = <0xf 0xfe140000 0 0x480>; 229 brg-frequency = <0>; 230 bus-frequency = <0>; 231 232 si1: si@700 { 233 compatible = "fsl,t1040-qe-si"; 234 reg = <0x700 0x80>; 235 }; 236 237 siram1: siram@1000 { 238 compatible = "fsl,t1040-qe-siram"; 239 reg = <0x1000 0x800>; 240 }; 241 242 ucc_hdlc: ucc@2000 { 243 compatible = "fsl,ucc-hdlc"; 244 rx-clock-name = "clk8"; 245 tx-clock-name = "clk9"; 246 fsl,rx-sync-clock = "rsync_pin"; 247 fsl,tx-sync-clock = "tsync_pin"; 248 fsl,tx-timeslot-mask = <0xfffffffe>; 249 fsl,rx-timeslot-mask = <0xfffffffe>; 250 fsl,tdm-framer-type = "e1"; 251 fsl,tdm-id = <0>; 252 fsl,siram-entry-id = <0>; 253 fsl,tdm-interface; 254 }; 255 256 ucc_serial: ucc@2200 { 257 compatible = "fsl,t1040-ucc-uart"; 258 port-number = <0>; 259 rx-clock-name = "brg2"; 260 tx-clock-name = "brg2"; 261 }; 262 }; 263}; 264