1/* 2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ] 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35mpic: pic@40000 { 36 interrupt-controller; 37 #address-cells = <0>; 38 #interrupt-cells = <4>; 39 reg = <0x40000 0x40000>; 40 compatible = "fsl,mpic"; 41 device_type = "open-pic"; 42 big-endian; 43 single-cpu-affinity; 44 last-interrupt-source = <255>; 45}; 46 47timer@41100 { 48 compatible = "fsl,mpic-global-timer"; 49 reg = <0x41100 0x100 0x41300 4>; 50 interrupts = <0 0 3 0 51 1 0 3 0 52 2 0 3 0 53 3 0 3 0>; 54}; 55 56message@41400 { 57 compatible = "fsl,mpic-v3.1-msgr"; 58 reg = <0x41400 0x200>; 59 interrupts = < 60 0xb0 2 0 0 61 0xb1 2 0 0 62 0xb2 2 0 0 63 0xb3 2 0 0>; 64}; 65 66msi@41600 { 67 compatible = "fsl,mpic-msi"; 68 reg = <0x41600 0x80>; 69 msi-available-ranges = <0 0x100>; 70 interrupts = < 71 0xe0 0 0 0 72 0xe1 0 0 0 73 0xe2 0 0 0 74 0xe3 0 0 0 75 0xe4 0 0 0 76 0xe5 0 0 0 77 0xe6 0 0 0 78 0xe7 0 0 0>; 79}; 80