1/* 2 * P2041 Silicon/SoC Device Tree Source (pre include) 3 * 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/dts-v1/; 36 37/include/ "e500mc_power_isa.dtsi" 38 39/ { 40 compatible = "fsl,P2041"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { 46 ccsr = &soc; 47 dcsr = &dcsr; 48 49 serial0 = &serial0; 50 serial1 = &serial1; 51 serial2 = &serial2; 52 serial3 = &serial3; 53 pci0 = &pci0; 54 pci1 = &pci1; 55 pci2 = &pci2; 56 usb0 = &usb0; 57 usb1 = &usb1; 58 dma0 = &dma0; 59 dma1 = &dma1; 60 sdhc = &sdhc; 61 msi0 = &msi0; 62 msi1 = &msi1; 63 msi2 = &msi2; 64 65 crypto = &crypto; 66 sec_jr0 = &sec_jr0; 67 sec_jr1 = &sec_jr1; 68 sec_jr2 = &sec_jr2; 69 sec_jr3 = &sec_jr3; 70 rtic_a = &rtic_a; 71 rtic_b = &rtic_b; 72 rtic_c = &rtic_c; 73 rtic_d = &rtic_d; 74 sec_mon = &sec_mon; 75 76 fman0 = &fman0; 77 ethernet0 = &enet0; 78 ethernet1 = &enet1; 79 ethernet2 = &enet2; 80 ethernet3 = &enet3; 81 ethernet4 = &enet4; 82 ethernet5 = &enet5; 83 }; 84 85 cpus { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 89 cpu0: PowerPC,e500mc@0 { 90 device_type = "cpu"; 91 reg = <0>; 92 clocks = <&clockgen 1 0>; 93 next-level-cache = <&L2_0>; 94 fsl,portid-mapping = <0x80000000>; 95 L2_0: l2-cache { 96 next-level-cache = <&cpc>; 97 }; 98 }; 99 cpu1: PowerPC,e500mc@1 { 100 device_type = "cpu"; 101 reg = <1>; 102 clocks = <&clockgen 1 1>; 103 next-level-cache = <&L2_1>; 104 fsl,portid-mapping = <0x40000000>; 105 L2_1: l2-cache { 106 next-level-cache = <&cpc>; 107 }; 108 }; 109 cpu2: PowerPC,e500mc@2 { 110 device_type = "cpu"; 111 reg = <2>; 112 clocks = <&clockgen 1 2>; 113 next-level-cache = <&L2_2>; 114 fsl,portid-mapping = <0x20000000>; 115 L2_2: l2-cache { 116 next-level-cache = <&cpc>; 117 }; 118 }; 119 cpu3: PowerPC,e500mc@3 { 120 device_type = "cpu"; 121 reg = <3>; 122 clocks = <&clockgen 1 3>; 123 next-level-cache = <&L2_3>; 124 fsl,portid-mapping = <0x10000000>; 125 L2_3: l2-cache { 126 next-level-cache = <&cpc>; 127 }; 128 }; 129 }; 130}; 131