1/* 2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 nor@0,0 { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 compatible = "cfi-flash"; 40 reg = <0x0 0x0 0x1000000>; 41 bank-width = <2>; 42 device-width = <1>; 43 44 partition@0 { 45 /* This location must not be altered */ 46 /* 256KB for Vitesse 7385 Switch firmware */ 47 reg = <0x0 0x00040000>; 48 label = "NOR Vitesse-7385 Firmware"; 49 read-only; 50 }; 51 52 partition@40000 { 53 /* 256KB for DTB Image */ 54 reg = <0x00040000 0x00040000>; 55 label = "NOR DTB Image"; 56 }; 57 58 partition@80000 { 59 /* 3.5 MB for Linux Kernel Image */ 60 reg = <0x00080000 0x00380000>; 61 label = "NOR Linux Kernel Image"; 62 }; 63 64 partition@400000 { 65 /* 11MB for JFFS2 based Root file System */ 66 reg = <0x00400000 0x00b00000>; 67 label = "NOR JFFS2 Root File System"; 68 }; 69 70 partition@f00000 { 71 /* This location must not be altered */ 72 /* 512KB for u-boot Bootloader Image */ 73 /* 512KB for u-boot Environment Variables */ 74 reg = <0x00f00000 0x00100000>; 75 label = "NOR U-Boot Image"; 76 read-only; 77 }; 78 }; 79 80 nand@1,0 { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 compatible = "fsl,p1025-fcm-nand", 84 "fsl,elbc-fcm-nand"; 85 reg = <0x1 0x0 0x40000>; 86 87 partition@0 { 88 /* This location must not be altered */ 89 /* 1MB for u-boot Bootloader Image */ 90 reg = <0x0 0x00100000>; 91 label = "NAND U-Boot Image"; 92 read-only; 93 }; 94 95 partition@100000 { 96 /* 1MB for DTB Image */ 97 reg = <0x00100000 0x00100000>; 98 label = "NAND DTB Image"; 99 }; 100 101 partition@200000 { 102 /* 4MB for Linux Kernel Image */ 103 reg = <0x00200000 0x00400000>; 104 label = "NAND Linux Kernel Image"; 105 }; 106 107 partition@600000 { 108 /* 4MB for Compressed Root file System Image */ 109 reg = <0x00600000 0x00400000>; 110 label = "NAND Compressed RFS Image"; 111 }; 112 113 partition@a00000 { 114 /* 7MB for JFFS2 based Root file System */ 115 reg = <0x00a00000 0x00700000>; 116 label = "NAND JFFS2 Root File System"; 117 }; 118 119 partition@1100000 { 120 /* 15MB for JFFS2 based Root file System */ 121 reg = <0x01100000 0x00f00000>; 122 label = "NAND Writable User area"; 123 }; 124 }; 125 126}; 127 128&soc { 129 i2c@3000 { 130 rtc@68 { 131 compatible = "dallas,ds1339"; 132 reg = <0x68>; 133 }; 134 }; 135 136 spi@7000 { 137 flash@0 { 138 #address-cells = <1>; 139 #size-cells = <1>; 140 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 141 reg = <0>; 142 spi-max-frequency = <40000000>; /* input clock */ 143 144 partition@u-boot { 145 /* 512KB for u-boot Bootloader Image */ 146 reg = <0x0 0x00080000>; 147 label = "u-boot"; 148 read-only; 149 }; 150 151 partition@dtb { 152 /* 512KB for DTB Image */ 153 reg = <0x00080000 0x00080000>; 154 label = "dtb"; 155 }; 156 157 partition@kernel { 158 /* 4MB for Linux Kernel Image */ 159 reg = <0x00100000 0x00400000>; 160 label = "kernel"; 161 }; 162 163 partition@fs { 164 /* 4MB for Compressed RFS Image */ 165 reg = <0x00500000 0x00400000>; 166 label = "file system"; 167 }; 168 169 partition@jffs-fs { 170 /* 7MB for JFFS2 based RFS */ 171 reg = <0x00900000 0x00700000>; 172 label = "file system jffs2"; 173 }; 174 }; 175 }; 176 177 usb@22000 { 178 phy_type = "ulpi"; 179 }; 180 181 /* USB2 is shared with localbus, so it must be disabled 182 by default. We can't put 'status = "disabled";' here 183 since U-Boot doesn't clear the status property when 184 it enables USB2. OTOH, U-Boot does create a new node 185 when there isn't any. So, just comment it out. 186 usb@23000 { 187 phy_type = "ulpi"; 188 }; 189 */ 190 191 mdio@24000 { 192 phy0: ethernet-phy@0 { 193 interrupt-parent = <&mpic>; 194 interrupts = <3 1>; 195 reg = <0x0>; 196 }; 197 198 phy1: ethernet-phy@1 { 199 interrupt-parent = <&mpic>; 200 interrupts = <2 1>; 201 reg = <0x1>; 202 }; 203 204 tbi0: tbi-phy@11 { 205 reg = <0x11>; 206 device_type = "tbi-phy"; 207 }; 208 }; 209 210 mdio@25000 { 211 tbi1: tbi-phy@11 { 212 reg = <0x11>; 213 device_type = "tbi-phy"; 214 }; 215 }; 216 217 mdio@26000 { 218 tbi2: tbi-phy@11 { 219 reg = <0x11>; 220 device_type = "tbi-phy"; 221 }; 222 }; 223 224 enet0: ethernet@b0000 { 225 fixed-link = <1 1 1000 0 0>; 226 phy-connection-type = "rgmii-id"; 227 228 }; 229 230 enet1: ethernet@b1000 { 231 phy-handle = <&phy0>; 232 tbi-handle = <&tbi1>; 233 phy-connection-type = "sgmii"; 234 }; 235 236 enet2: ethernet@b2000 { 237 phy-handle = <&phy1>; 238 phy-connection-type = "rgmii-id"; 239 }; 240 241 par_io@e0100 { 242 #address-cells = <1>; 243 #size-cells = <1>; 244 reg = <0xe0100 0x60>; 245 ranges = <0x0 0xe0100 0x60>; 246 device_type = "par_io"; 247 num-ports = <3>; 248 pio1: ucc_pin@1 { 249 pio-map = < 250 /* port pin dir open_drain assignment has_irq */ 251 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 252 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 253 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 254 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ 255 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 256 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 257 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 258 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 259 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ 260 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ 261 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 262 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 263 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 264 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ 265 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 266 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ 267 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ 268 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ 269 }; 270 271 pio2: ucc_pin@2 { 272 pio-map = < 273 /* port pin dir open_drain assignment has_irq */ 274 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 275 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 276 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ 277 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ 278 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ 279 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ 280 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ 281 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ 282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ 283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ 284 }; 285 286 pio3: ucc_pin@3 { 287 pio-map = < 288 /* port pin dir open_drain assignment has_irq */ 289 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/ 290 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/ 291 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/ 292 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/ 293 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/ 294 }; 295 296 pio4: ucc_pin@4 { 297 pio-map = < 298 /* port pin dir open_drain assignment has_irq */ 299 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/ 300 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/ 301 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/ 302 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/ 303 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/ 304 }; 305 }; 306}; 307 308&qe { 309 serial2: ucc@2600 { 310 device_type = "serial"; 311 compatible = "ucc_uart"; 312 port-number = <0>; 313 rx-clock-name = "brg6"; 314 tx-clock-name = "brg6"; 315 pio-handle = <&pio3>; 316 }; 317 318 serial3: ucc@2200 { 319 device_type = "serial"; 320 compatible = "ucc_uart"; 321 port-number = <1>; 322 rx-clock-name = "brg2"; 323 tx-clock-name = "brg2"; 324 pio-handle = <&pio4>; 325 }; 326}; 327