1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * P1021 MDS Device Tree Source 4 * 5 * Copyright 2010,2012 Freescale Semiconductor Inc. 6 */ 7 8/include/ "p1021si-pre.dtsi" 9/ { 10 model = "fsl,P1021"; 11 compatible = "fsl,P1021MDS"; 12 13 aliases { 14 ethernet3 = &enet3; 15 ethernet4 = &enet4; 16 }; 17 18 memory { 19 device_type = "memory"; 20 }; 21 22 lbc: localbus@ffe05000 { 23 reg = <0x0 0xffe05000 0x0 0x1000>; 24 25 /* NAND Flash, BCSR, PMC0/1*/ 26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 27 0x1 0x0 0x0 0xf8000000 0x00008000 28 0x2 0x0 0x0 0xf8010000 0x00020000 29 0x3 0x0 0x0 0xf8020000 0x00020000>; 30 31 nand@0,0 { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "fsl,p1021-fcm-nand", 35 "fsl,elbc-fcm-nand"; 36 reg = <0x0 0x0 0x40000>; 37 38 partition@0 { 39 /* This location must not be altered */ 40 /* 1MB for u-boot Bootloader Image */ 41 reg = <0x0 0x00100000>; 42 label = "NAND (RO) U-Boot Image"; 43 read-only; 44 }; 45 46 partition@100000 { 47 /* 1MB for DTB Image */ 48 reg = <0x00100000 0x00100000>; 49 label = "NAND (RO) DTB Image"; 50 read-only; 51 }; 52 53 partition@200000 { 54 /* 4MB for Linux Kernel Image */ 55 reg = <0x00200000 0x00400000>; 56 label = "NAND (RO) Linux Kernel Image"; 57 read-only; 58 }; 59 60 partition@600000 { 61 /* 5MB for Compressed Root file System Image */ 62 reg = <0x00600000 0x00500000>; 63 label = "NAND (RO) Compressed RFS Image"; 64 read-only; 65 }; 66 67 partition@b00000 { 68 /* 6MB for JFFS2 based Root file System */ 69 reg = <0x00a00000 0x00600000>; 70 label = "NAND (RW) JFFS2 Root File System"; 71 }; 72 73 partition@1100000 { 74 /* 14MB for JFFS2 based Root file System */ 75 reg = <0x01100000 0x00e00000>; 76 label = "NAND (RW) Writable User area"; 77 }; 78 79 partition@1f00000 { 80 /* 1MB for microcode */ 81 reg = <0x01f00000 0x00100000>; 82 label = "NAND (RO) QE Ucode"; 83 read-only; 84 }; 85 }; 86 87 bcsr@1,0 { 88 #address-cells = <1>; 89 #size-cells = <1>; 90 compatible = "fsl,p1021mds-bcsr"; 91 reg = <1 0 0x8000>; 92 ranges = <0 1 0 0x8000>; 93 }; 94 95 pib@2,0 { 96 compatible = "fsl,p1021mds-pib"; 97 reg = <2 0 0x10000>; 98 }; 99 100 pib@3,0 { 101 compatible = "fsl,p1021mds-pib"; 102 reg = <3 0 0x10000>; 103 }; 104 }; 105 106 soc: soc@ffe00000 { 107 compatible = "fsl,p1021-immr", "simple-bus"; 108 ranges = <0x0 0x0 0xffe00000 0x100000>; 109 110 i2c@3000 { 111 rtc@68 { 112 compatible = "dallas,ds1374"; 113 reg = <0x68>; 114 }; 115 }; 116 117 spi@7000 { 118 119 flash@0 { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 123 reg = <0>; 124 spi-max-frequency = <40000000>; /* input clock */ 125 126 partition@u-boot { 127 label = "u-boot-spi"; 128 reg = <0x00000000 0x00100000>; 129 read-only; 130 }; 131 partition@kernel { 132 label = "kernel-spi"; 133 reg = <0x00100000 0x00500000>; 134 read-only; 135 }; 136 partition@dtb { 137 label = "dtb-spi"; 138 reg = <0x00600000 0x00100000>; 139 read-only; 140 }; 141 partition@fs { 142 label = "file system-spi"; 143 reg = <0x00700000 0x00900000>; 144 }; 145 }; 146 }; 147 148 usb@22000 { 149 phy_type = "ulpi"; 150 dr_mode = "host"; 151 }; 152 153 mdio@24000 { 154 phy0: ethernet-phy@0 { 155 interrupts = <1 1 0 0>; 156 reg = <0x0>; 157 }; 158 phy1: ethernet-phy@1 { 159 interrupts = <2 1 0 0>; 160 reg = <0x1>; 161 }; 162 phy4: ethernet-phy@4 { 163 reg = <0x4>; 164 }; 165 tbi-phy@5 { 166 device_type = "tbi-phy"; 167 reg = <0x5>; 168 }; 169 }; 170 171 mdio@25000 { 172 tbi0: tbi-phy@11 { 173 reg = <0x11>; 174 device_type = "tbi-phy"; 175 }; 176 }; 177 178 ethernet@b0000 { 179 phy-handle = <&phy0>; 180 phy-connection-type = "rgmii-id"; 181 }; 182 183 ethernet@b1000 { 184 phy-handle = <&phy4>; 185 tbi-handle = <&tbi0>; 186 phy-connection-type = "sgmii"; 187 }; 188 189 ethernet@b2000 { 190 phy-handle = <&phy1>; 191 phy-connection-type = "rgmii-id"; 192 }; 193 194 par_io@e0100 { 195 #address-cells = <1>; 196 #size-cells = <1>; 197 reg = <0xe0100 0x60>; 198 ranges = <0x0 0xe0100 0x60>; 199 device_type = "par_io"; 200 num-ports = <3>; 201 pio1: ucc_pin@1 { 202 pio-map = < 203 /* port pin dir open_drain assignment has_irq */ 204 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 205 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 206 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 207 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ 208 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 209 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 210 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 211 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 212 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ 213 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ 214 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 215 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 216 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 217 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ 218 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 219 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ 220 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ 221 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ 222 }; 223 224 pio2: ucc_pin@2 { 225 pio-map = < 226 /* port pin dir open_drain assignment has_irq */ 227 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 228 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 229 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ 230 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ 231 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ 232 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ 233 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ 234 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ 235 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ 236 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ 237 }; 238 }; 239 }; 240 241 pci0: pcie@ffe09000 { 242 reg = <0 0xffe09000 0 0x1000>; 243 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 244 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 245 pcie@0 { 246 ranges = <0x2000000 0x0 0xa0000000 247 0x2000000 0x0 0xa0000000 248 0x0 0x20000000 249 250 0x1000000 0x0 0x0 251 0x1000000 0x0 0x0 252 0x0 0x100000>; 253 }; 254 }; 255 256 pci1: pcie@ffe0a000 { 257 reg = <0 0xffe0a000 0 0x1000>; 258 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 259 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 260 pcie@0 { 261 ranges = <0x2000000 0x0 0xc0000000 262 0x2000000 0x0 0xc0000000 263 0x0 0x20000000 264 265 0x1000000 0x0 0x0 266 0x1000000 0x0 0x0 267 0x0 0x100000>; 268 }; 269 }; 270 271 qe: qe@ffe80000 { 272 ranges = <0x0 0x0 0xffe80000 0x40000>; 273 reg = <0 0xffe80000 0 0x480>; 274 brg-frequency = <0>; 275 bus-frequency = <0>; 276 status = "disabled"; /* no firmware loaded */ 277 278 enet3: ucc@2000 { 279 device_type = "network"; 280 compatible = "ucc_geth"; 281 local-mac-address = [ 00 00 00 00 00 00 ]; 282 rx-clock-name = "clk12"; 283 tx-clock-name = "clk9"; 284 pio-handle = <&pio1>; 285 phy-handle = <&qe_phy0>; 286 phy-connection-type = "mii"; 287 }; 288 289 mdio@2120 { 290 qe_phy0: ethernet-phy@0 { 291 interrupt-parent = <&mpic>; 292 interrupts = <4 1 0 0>; 293 reg = <0x0>; 294 }; 295 qe_phy1: ethernet-phy@3 { 296 interrupt-parent = <&mpic>; 297 interrupts = <5 1 0 0>; 298 reg = <0x3>; 299 }; 300 tbi-phy@11 { 301 reg = <0x11>; 302 device_type = "tbi-phy"; 303 }; 304 }; 305 306 enet4: ucc@2400 { 307 device_type = "network"; 308 compatible = "ucc_geth"; 309 local-mac-address = [ 00 00 00 00 00 00 ]; 310 rx-clock-name = "none"; 311 tx-clock-name = "clk13"; 312 pio-handle = <&pio2>; 313 phy-handle = <&qe_phy1>; 314 phy-connection-type = "rmii"; 315 }; 316 }; 317}; 318 319/include/ "p1021si-post.dtsi" 320