1/* 2 * P1020 RDB-PD Device Tree Source (32-bit address map) 3 * 4 * Copyright 2013 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p1020si-pre.dtsi" 36/ { 37 model = "fsl,P1020RDB-PD"; 38 compatible = "fsl,P1020RDB-PD"; 39 40 memory { 41 device_type = "memory"; 42 }; 43 44 lbc: localbus@ffe05000 { 45 reg = <0x0 0xffe05000 0x0 0x1000>; 46 47 /* NOR, NAND flash, L2 switch and CPLD */ 48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000 49 0x1 0x0 0x0 0xff800000 0x00040000 50 0x2 0x0 0x0 0xffa00000 0x00020000 51 0x3 0x0 0x0 0xffb00000 0x00020000>; 52 53 nor@0,0 { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 compatible = "cfi-flash"; 57 reg = <0x0 0x0 0x4000000>; 58 bank-width = <2>; 59 device-width = <1>; 60 61 partition@0 { 62 /* 128KB for DTB Image */ 63 reg = <0x0 0x00020000>; 64 label = "NOR DTB Image"; 65 }; 66 67 partition@20000 { 68 /* 3.875 MB for Linux Kernel Image */ 69 reg = <0x00020000 0x003e0000>; 70 label = "NOR Linux Kernel Image"; 71 }; 72 73 partition@400000 { 74 /* 58MB for Root file System */ 75 reg = <0x00400000 0x03a00000>; 76 label = "NOR Root File System"; 77 }; 78 79 partition@3e00000 { 80 /* This location must not be altered */ 81 /* 1M for Vitesse 7385 Switch firmware */ 82 reg = <0x3e00000 0x00100000>; 83 label = "NOR Vitesse-7385 Firmware"; 84 read-only; 85 }; 86 87 partition@3f00000 { 88 /* This location must not be altered */ 89 /* 512KB for u-boot Bootloader Image */ 90 /* 512KB for u-boot Environment Variables */ 91 reg = <0x03f00000 0x00100000>; 92 label = "NOR U-Boot Image"; 93 read-only; 94 }; 95 }; 96 97 nand@1,0 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "fsl,p1020-fcm-nand", 101 "fsl,elbc-fcm-nand"; 102 reg = <0x1 0x0 0x40000>; 103 104 partition@0 { 105 /* This location must not be altered */ 106 /* 1MB for u-boot Bootloader Image */ 107 reg = <0x0 0x00100000>; 108 label = "NAND U-Boot Image"; 109 read-only; 110 }; 111 112 partition@100000 { 113 /* 1MB for DTB Image */ 114 reg = <0x00100000 0x00100000>; 115 label = "NAND DTB Image"; 116 }; 117 118 partition@200000 { 119 /* 4MB for Linux Kernel Image */ 120 reg = <0x00200000 0x00400000>; 121 label = "NAND Linux Kernel Image"; 122 }; 123 124 partition@600000 { 125 /* 122MB for File System Image */ 126 reg = <0x00600000 0x07a00000>; 127 label = "NAND File System Image"; 128 }; 129 }; 130 131 cpld@2,0 { 132 compatible = "fsl,p1020rdb-pd-cpld"; 133 reg = <0x2 0x0 0x20000>; 134 }; 135 136 L2switch@3,0 { 137 #address-cells = <1>; 138 #size-cells = <1>; 139 compatible = "vitesse-7385"; 140 reg = <0x3 0x0 0x20000>; 141 }; 142 }; 143 144 soc: soc@ffe00000 { 145 ranges = <0x0 0x0 0xffe00000 0x100000>; 146 147 i2c@3000 { 148 rtc@68 { 149 compatible = "dallas,ds1339"; 150 reg = <0x68>; 151 }; 152 }; 153 154 spi@7000 { 155 flash@0 { 156 #address-cells = <1>; 157 #size-cells = <1>; 158 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 159 reg = <0>; 160 /* input clock */ 161 spi-max-frequency = <40000000>; 162 163 partition@0 { 164 /* 512KB for u-boot Bootloader Image */ 165 reg = <0x0 0x00080000>; 166 label = "SPI U-Boot Image"; 167 read-only; 168 }; 169 170 partition@80000 { 171 /* 512KB for DTB Image*/ 172 reg = <0x00080000 0x00080000>; 173 label = "SPI DTB Image"; 174 }; 175 176 partition@100000 { 177 /* 4MB for Linux Kernel Image */ 178 reg = <0x00100000 0x00400000>; 179 label = "SPI Linux Kernel Image"; 180 }; 181 182 partition@500000 { 183 /* 11MB for FS System Image */ 184 reg = <0x00500000 0x00b00000>; 185 label = "SPI File System Image"; 186 }; 187 }; 188 189 slic@0 { 190 compatible = "zarlink,le88266"; 191 reg = <1>; 192 spi-max-frequency = <8000000>; 193 }; 194 195 slic@1 { 196 compatible = "zarlink,le88266"; 197 reg = <2>; 198 spi-max-frequency = <8000000>; 199 }; 200 }; 201 202 mdio@24000 { 203 phy0: ethernet-phy@0 { 204 interrupts = <3 1 0 0>; 205 reg = <0x0>; 206 }; 207 208 phy1: ethernet-phy@1 { 209 interrupts = <2 1 0 0>; 210 reg = <0x1>; 211 }; 212 }; 213 214 mdio@25000 { 215 tbi1: tbi-phy@11 { 216 reg = <0x11>; 217 device_type = "tbi-phy"; 218 }; 219 }; 220 221 mdio@26000 { 222 tbi2: tbi-phy@11 { 223 reg = <0x11>; 224 device_type = "tbi-phy"; 225 }; 226 }; 227 228 ptp_clock@b0e00 { 229 compatible = "fsl,etsec-ptp"; 230 reg = <0xb0e00 0xb0>; 231 interrupts = <68 2 0 0 69 2 0 0>; 232 fsl,tclk-period = <10>; 233 fsl,tmr-prsc = <2>; 234 fsl,tmr-add = <0x80000016>; 235 fsl,tmr-fiper1 = <999999990>; 236 fsl,tmr-fiper2 = <99990>; 237 fsl,max-adj = <199999999>; 238 }; 239 240 enet0: ethernet@b0000 { 241 fixed-link = <1 1 1000 0 0>; 242 phy-connection-type = "rgmii-id"; 243 }; 244 245 enet1: ethernet@b1000 { 246 phy-handle = <&phy0>; 247 tbi-handle = <&tbi1>; 248 phy-connection-type = "sgmii"; 249 }; 250 251 enet2: ethernet@b2000 { 252 phy-handle = <&phy1>; 253 phy-connection-type = "rgmii-id"; 254 }; 255 256 usb@22000 { 257 phy_type = "ulpi"; 258 }; 259 }; 260 261 pci0: pcie@ffe09000 { 262 reg = <0x0 0xffe09000 0x0 0x1000>; 263 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000 264 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>; 265 pcie@0 { 266 ranges = <0x2000000 0x0 0xa0000000 267 0x2000000 0x0 0xa0000000 268 0x0 0x20000000 269 270 0x1000000 0x0 0x0 271 0x1000000 0x0 0x0 272 0x0 0x100000>; 273 }; 274 }; 275 276 pci1: pcie@ffe0a000 { 277 reg = <0x0 0xffe0a000 0x0 0x1000>; 278 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000 279 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>; 280 pcie@0 { 281 ranges = <0x2000000 0x0 0x80000000 282 0x2000000 0x0 0x80000000 283 0x0 0x20000000 284 285 0x1000000 0x0 0x0 286 0x1000000 0x0 0x0 287 0x0 0x100000>; 288 }; 289 }; 290}; 291 292/include/ "p1020si-post.dtsi" 293