1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8540 ADS Device Tree Source 4 * 5 * Copyright 2006, 2008 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9 10/include/ "e500v1_power_isa.dtsi" 11 12/ { 13 model = "MPC8540ADS"; 14 compatible = "MPC8540ADS", "MPC85xxADS"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 ethernet0 = &enet0; 20 ethernet1 = &enet1; 21 ethernet2 = &enet2; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8540@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; // 32 bytes 35 i-cache-line-size = <32>; // 32 bytes 36 d-cache-size = <0x8000>; // L1, 32K 37 i-cache-size = <0x8000>; // L1, 32K 38 timebase-frequency = <0>; // 33 MHz, from uboot 39 bus-frequency = <0>; // 166 MHz 40 clock-frequency = <0>; // 825 MHz, from uboot 41 next-level-cache = <&L2>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x0 0x8000000>; // 128M at 0x0 48 }; 49 50 soc8540@e0000000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 device_type = "soc"; 54 compatible = "simple-bus"; 55 ranges = <0x0 0xe0000000 0x100000>; 56 bus-frequency = <0>; 57 58 ecm-law@0 { 59 compatible = "fsl,ecm-law"; 60 reg = <0x0 0x1000>; 61 fsl,num-laws = <8>; 62 }; 63 64 ecm@1000 { 65 compatible = "fsl,mpc8540-ecm", "fsl,ecm"; 66 reg = <0x1000 0x1000>; 67 interrupts = <17 2>; 68 interrupt-parent = <&mpic>; 69 }; 70 71 memory-controller@2000 { 72 compatible = "fsl,mpc8540-memory-controller"; 73 reg = <0x2000 0x1000>; 74 interrupt-parent = <&mpic>; 75 interrupts = <18 2>; 76 }; 77 78 L2: l2-cache-controller@20000 { 79 compatible = "fsl,mpc8540-l2-cache-controller"; 80 reg = <0x20000 0x1000>; 81 cache-line-size = <32>; // 32 bytes 82 cache-size = <0x40000>; // L2, 256K 83 interrupt-parent = <&mpic>; 84 interrupts = <16 2>; 85 }; 86 87 i2c@3000 { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 cell-index = <0>; 91 compatible = "fsl-i2c"; 92 reg = <0x3000 0x100>; 93 interrupts = <43 2>; 94 interrupt-parent = <&mpic>; 95 dfsrr; 96 }; 97 98 dma@21300 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 102 reg = <0x21300 0x4>; 103 ranges = <0x0 0x21100 0x200>; 104 cell-index = <0>; 105 dma-channel@0 { 106 compatible = "fsl,mpc8540-dma-channel", 107 "fsl,eloplus-dma-channel"; 108 reg = <0x0 0x80>; 109 cell-index = <0>; 110 interrupt-parent = <&mpic>; 111 interrupts = <20 2>; 112 }; 113 dma-channel@80 { 114 compatible = "fsl,mpc8540-dma-channel", 115 "fsl,eloplus-dma-channel"; 116 reg = <0x80 0x80>; 117 cell-index = <1>; 118 interrupt-parent = <&mpic>; 119 interrupts = <21 2>; 120 }; 121 dma-channel@100 { 122 compatible = "fsl,mpc8540-dma-channel", 123 "fsl,eloplus-dma-channel"; 124 reg = <0x100 0x80>; 125 cell-index = <2>; 126 interrupt-parent = <&mpic>; 127 interrupts = <22 2>; 128 }; 129 dma-channel@180 { 130 compatible = "fsl,mpc8540-dma-channel", 131 "fsl,eloplus-dma-channel"; 132 reg = <0x180 0x80>; 133 cell-index = <3>; 134 interrupt-parent = <&mpic>; 135 interrupts = <23 2>; 136 }; 137 }; 138 139 enet0: ethernet@24000 { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 cell-index = <0>; 143 device_type = "network"; 144 model = "TSEC"; 145 compatible = "gianfar"; 146 reg = <0x24000 0x1000>; 147 ranges = <0x0 0x24000 0x1000>; 148 local-mac-address = [ 00 00 00 00 00 00 ]; 149 interrupts = <29 2 30 2 34 2>; 150 interrupt-parent = <&mpic>; 151 tbi-handle = <&tbi0>; 152 phy-handle = <&phy0>; 153 154 mdio@520 { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "fsl,gianfar-mdio"; 158 reg = <0x520 0x20>; 159 160 phy0: ethernet-phy@0 { 161 interrupt-parent = <&mpic>; 162 interrupts = <5 1>; 163 reg = <0x0>; 164 }; 165 phy1: ethernet-phy@1 { 166 interrupt-parent = <&mpic>; 167 interrupts = <5 1>; 168 reg = <0x1>; 169 }; 170 phy3: ethernet-phy@3 { 171 interrupt-parent = <&mpic>; 172 interrupts = <7 1>; 173 reg = <0x3>; 174 }; 175 tbi0: tbi-phy@11 { 176 reg = <0x11>; 177 device_type = "tbi-phy"; 178 }; 179 }; 180 }; 181 182 enet1: ethernet@25000 { 183 #address-cells = <1>; 184 #size-cells = <1>; 185 cell-index = <1>; 186 device_type = "network"; 187 model = "TSEC"; 188 compatible = "gianfar"; 189 reg = <0x25000 0x1000>; 190 ranges = <0x0 0x25000 0x1000>; 191 local-mac-address = [ 00 00 00 00 00 00 ]; 192 interrupts = <35 2 36 2 40 2>; 193 interrupt-parent = <&mpic>; 194 tbi-handle = <&tbi1>; 195 phy-handle = <&phy1>; 196 197 mdio@520 { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 compatible = "fsl,gianfar-tbi"; 201 reg = <0x520 0x20>; 202 203 tbi1: tbi-phy@11 { 204 reg = <0x11>; 205 device_type = "tbi-phy"; 206 }; 207 }; 208 }; 209 210 enet2: ethernet@26000 { 211 #address-cells = <1>; 212 #size-cells = <1>; 213 cell-index = <2>; 214 device_type = "network"; 215 model = "FEC"; 216 compatible = "gianfar"; 217 reg = <0x26000 0x1000>; 218 ranges = <0x0 0x26000 0x1000>; 219 local-mac-address = [ 00 00 00 00 00 00 ]; 220 interrupts = <41 2>; 221 interrupt-parent = <&mpic>; 222 tbi-handle = <&tbi2>; 223 phy-handle = <&phy3>; 224 225 mdio@520 { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 compatible = "fsl,gianfar-tbi"; 229 reg = <0x520 0x20>; 230 231 tbi2: tbi-phy@11 { 232 reg = <0x11>; 233 device_type = "tbi-phy"; 234 }; 235 }; 236 }; 237 238 serial0: serial@4500 { 239 cell-index = <0>; 240 device_type = "serial"; 241 compatible = "fsl,ns16550", "ns16550"; 242 reg = <0x4500 0x100>; // reg base, size 243 clock-frequency = <0>; // should we fill in in uboot? 244 interrupts = <42 2>; 245 interrupt-parent = <&mpic>; 246 }; 247 248 serial1: serial@4600 { 249 cell-index = <1>; 250 device_type = "serial"; 251 compatible = "fsl,ns16550", "ns16550"; 252 reg = <0x4600 0x100>; // reg base, size 253 clock-frequency = <0>; // should we fill in in uboot? 254 interrupts = <42 2>; 255 interrupt-parent = <&mpic>; 256 }; 257 mpic: pic@40000 { 258 interrupt-controller; 259 #address-cells = <0>; 260 #interrupt-cells = <2>; 261 reg = <0x40000 0x40000>; 262 compatible = "chrp,open-pic"; 263 device_type = "open-pic"; 264 }; 265 }; 266 267 pci0: pci@e0008000 { 268 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 269 interrupt-map = < 270 271 /* IDSEL 0x02 */ 272 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 273 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 274 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 275 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 276 277 /* IDSEL 0x03 */ 278 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 279 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 280 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 281 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 282 283 /* IDSEL 0x04 */ 284 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 285 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 286 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 287 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 288 289 /* IDSEL 0x05 */ 290 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 291 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 292 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 293 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 294 295 /* IDSEL 0x0c */ 296 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 297 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 298 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 299 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 300 301 /* IDSEL 0x0d */ 302 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 303 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 304 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 305 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 306 307 /* IDSEL 0x0e */ 308 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 309 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 310 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 311 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 312 313 /* IDSEL 0x0f */ 314 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 315 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 316 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 317 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 318 319 /* IDSEL 0x12 */ 320 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 321 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 322 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 323 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 324 325 /* IDSEL 0x13 */ 326 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 327 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 328 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 329 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 330 331 /* IDSEL 0x14 */ 332 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 333 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 334 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 335 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 336 337 /* IDSEL 0x15 */ 338 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 339 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 340 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 341 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; 342 interrupt-parent = <&mpic>; 343 interrupts = <24 2>; 344 bus-range = <0 0>; 345 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 346 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; 347 clock-frequency = <66666666>; 348 #interrupt-cells = <1>; 349 #size-cells = <2>; 350 #address-cells = <3>; 351 reg = <0xe0008000 0x1000>; 352 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 353 device_type = "pci"; 354 }; 355}; 356