1/* 2 * B4420 Silicon/SoC Device Tree Source (pre include) 3 * 4 * Copyright 2012 - 2015 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of 32 * this software, even if advised of the possibility of such damage. 33 */ 34 35/dts-v1/; 36 37/include/ "e6500_power_isa.dtsi" 38 39/ { 40 compatible = "fsl,B4420"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { 46 ccsr = &soc; 47 dcsr = &dcsr; 48 49 serial0 = &serial0; 50 serial1 = &serial1; 51 serial2 = &serial2; 52 serial3 = &serial3; 53 pci0 = &pci0; 54 usb0 = &usb0; 55 dma0 = &dma0; 56 dma1 = &dma1; 57 sdhc = &sdhc; 58 59 fman0 = &fman0; 60 ethernet0 = &enet0; 61 ethernet1 = &enet1; 62 ethernet2 = &enet2; 63 ethernet3 = &enet3; 64 }; 65 66 cpus { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 70 cpu0: PowerPC,e6500@0 { 71 device_type = "cpu"; 72 reg = <0 1>; 73 clocks = <&clockgen 1 0>; 74 next-level-cache = <&L2_1>; 75 fsl,portid-mapping = <0x80000000>; 76 }; 77 cpu1: PowerPC,e6500@2 { 78 device_type = "cpu"; 79 reg = <2 3>; 80 clocks = <&clockgen 1 0>; 81 next-level-cache = <&L2_1>; 82 fsl,portid-mapping = <0x80000000>; 83 }; 84 }; 85}; 86