1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 4 */ 5#include <dt-bindings/clock/microchip,pic32-clock.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&evic>; 12 13 aliases { 14 gpio0 = &gpio0; 15 gpio1 = &gpio1; 16 gpio2 = &gpio2; 17 gpio3 = &gpio3; 18 gpio4 = &gpio4; 19 gpio5 = &gpio5; 20 gpio6 = &gpio6; 21 gpio7 = &gpio7; 22 gpio8 = &gpio8; 23 gpio9 = &gpio9; 24 serial0 = &uart1; 25 serial1 = &uart2; 26 serial2 = &uart3; 27 serial3 = &uart4; 28 serial4 = &uart5; 29 serial5 = &uart6; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 compatible = "mti,mips14KEc"; 38 device_type = "cpu"; 39 }; 40 }; 41 42 soc { 43 compatible = "microchip,pic32mzda-infra"; 44 interrupts = <0 IRQ_TYPE_EDGE_RISING>; 45 }; 46 47 /* external clock input on TxCLKI pin */ 48 txcki: txcki_clk { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <4000000>; 52 status = "disabled"; 53 }; 54 55 /* external input on REFCLKIx pin */ 56 refix: refix_clk { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 status = "disabled"; 61 }; 62 63 rootclk: clock-controller@1f801200 { 64 compatible = "microchip,pic32mzda-clk"; 65 reg = <0x1f801200 0x200>; 66 #clock-cells = <1>; 67 microchip,pic32mzda-sosc; 68 }; 69 70 evic: interrupt-controller@1f810000 { 71 compatible = "microchip,pic32mzda-evic"; 72 interrupt-controller; 73 #interrupt-cells = <2>; 74 reg = <0x1f810000 0x1000>; 75 microchip,external-irqs = <3 8 13 18 23>; 76 }; 77 78 pic32_pinctrl: pinctrl@1f801400{ 79 #address-cells = <1>; 80 #size-cells = <1>; 81 compatible = "microchip,pic32mzda-pinctrl"; 82 reg = <0x1f801400 0x400>; 83 clocks = <&rootclk PB1CLK>; 84 }; 85 86 /* PORTA */ 87 gpio0: gpio0@1f860000 { 88 compatible = "microchip,pic32mzda-gpio"; 89 reg = <0x1f860000 0x100>; 90 interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; 91 #gpio-cells = <2>; 92 gpio-controller; 93 interrupt-controller; 94 #interrupt-cells = <2>; 95 clocks = <&rootclk PB4CLK>; 96 microchip,gpio-bank = <0>; 97 gpio-ranges = <&pic32_pinctrl 0 0 16>; 98 }; 99 100 /* PORTB */ 101 gpio1: gpio1@1f860100 { 102 compatible = "microchip,pic32mzda-gpio"; 103 reg = <0x1f860100 0x100>; 104 interrupts = <119 IRQ_TYPE_LEVEL_HIGH>; 105 #gpio-cells = <2>; 106 gpio-controller; 107 interrupt-controller; 108 #interrupt-cells = <2>; 109 clocks = <&rootclk PB4CLK>; 110 microchip,gpio-bank = <1>; 111 gpio-ranges = <&pic32_pinctrl 0 16 16>; 112 }; 113 114 /* PORTC */ 115 gpio2: gpio2@1f860200 { 116 compatible = "microchip,pic32mzda-gpio"; 117 reg = <0x1f860200 0x100>; 118 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; 119 #gpio-cells = <2>; 120 gpio-controller; 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 clocks = <&rootclk PB4CLK>; 124 microchip,gpio-bank = <2>; 125 gpio-ranges = <&pic32_pinctrl 0 32 16>; 126 }; 127 128 /* PORTD */ 129 gpio3: gpio3@1f860300 { 130 compatible = "microchip,pic32mzda-gpio"; 131 reg = <0x1f860300 0x100>; 132 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; 133 #gpio-cells = <2>; 134 gpio-controller; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 clocks = <&rootclk PB4CLK>; 138 microchip,gpio-bank = <3>; 139 gpio-ranges = <&pic32_pinctrl 0 48 16>; 140 }; 141 142 /* PORTE */ 143 gpio4: gpio4@1f860400 { 144 compatible = "microchip,pic32mzda-gpio"; 145 reg = <0x1f860400 0x100>; 146 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; 147 #gpio-cells = <2>; 148 gpio-controller; 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 clocks = <&rootclk PB4CLK>; 152 microchip,gpio-bank = <4>; 153 gpio-ranges = <&pic32_pinctrl 0 64 16>; 154 }; 155 156 /* PORTF */ 157 gpio5: gpio5@1f860500 { 158 compatible = "microchip,pic32mzda-gpio"; 159 reg = <0x1f860500 0x100>; 160 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; 161 #gpio-cells = <2>; 162 gpio-controller; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 clocks = <&rootclk PB4CLK>; 166 microchip,gpio-bank = <5>; 167 gpio-ranges = <&pic32_pinctrl 0 80 16>; 168 }; 169 170 /* PORTG */ 171 gpio6: gpio6@1f860600 { 172 compatible = "microchip,pic32mzda-gpio"; 173 reg = <0x1f860600 0x100>; 174 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; 175 #gpio-cells = <2>; 176 gpio-controller; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 clocks = <&rootclk PB4CLK>; 180 microchip,gpio-bank = <6>; 181 gpio-ranges = <&pic32_pinctrl 0 96 16>; 182 }; 183 184 /* PORTH */ 185 gpio7: gpio7@1f860700 { 186 compatible = "microchip,pic32mzda-gpio"; 187 reg = <0x1f860700 0x100>; 188 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 189 #gpio-cells = <2>; 190 gpio-controller; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 clocks = <&rootclk PB4CLK>; 194 microchip,gpio-bank = <7>; 195 gpio-ranges = <&pic32_pinctrl 0 112 16>; 196 }; 197 198 /* PORTI does not exist */ 199 200 /* PORTJ */ 201 gpio8: gpio8@1f860800 { 202 compatible = "microchip,pic32mzda-gpio"; 203 reg = <0x1f860800 0x100>; 204 interrupts = <126 IRQ_TYPE_LEVEL_HIGH>; 205 #gpio-cells = <2>; 206 gpio-controller; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 clocks = <&rootclk PB4CLK>; 210 microchip,gpio-bank = <8>; 211 gpio-ranges = <&pic32_pinctrl 0 128 16>; 212 }; 213 214 /* PORTK */ 215 gpio9: gpio9@1f860900 { 216 compatible = "microchip,pic32mzda-gpio"; 217 reg = <0x1f860900 0x100>; 218 interrupts = <127 IRQ_TYPE_LEVEL_HIGH>; 219 #gpio-cells = <2>; 220 gpio-controller; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 clocks = <&rootclk PB4CLK>; 224 microchip,gpio-bank = <9>; 225 gpio-ranges = <&pic32_pinctrl 0 144 16>; 226 }; 227 228 sdhci: sdhci@1f8ec000 { 229 compatible = "microchip,pic32mzda-sdhci"; 230 reg = <0x1f8ec000 0x100>; 231 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; 233 clock-names = "base_clk", "sys_clk"; 234 bus-width = <4>; 235 cap-sd-highspeed; 236 status = "disabled"; 237 }; 238 239 uart1: serial@1f822000 { 240 compatible = "microchip,pic32mzda-uart"; 241 reg = <0x1f822000 0x50>; 242 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, 243 <113 IRQ_TYPE_LEVEL_HIGH>, 244 <114 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&rootclk PB2CLK>; 246 status = "disabled"; 247 }; 248 249 uart2: serial@1f822200 { 250 compatible = "microchip,pic32mzda-uart"; 251 reg = <0x1f822200 0x50>; 252 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, 253 <146 IRQ_TYPE_LEVEL_HIGH>, 254 <147 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&rootclk PB2CLK>; 256 status = "disabled"; 257 }; 258 259 uart3: serial@1f822400 { 260 compatible = "microchip,pic32mzda-uart"; 261 reg = <0x1f822400 0x50>; 262 interrupts = <157 IRQ_TYPE_LEVEL_HIGH>, 263 <158 IRQ_TYPE_LEVEL_HIGH>, 264 <159 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&rootclk PB2CLK>; 266 status = "disabled"; 267 }; 268 269 uart4: serial@1f822600 { 270 compatible = "microchip,pic32mzda-uart"; 271 reg = <0x1f822600 0x50>; 272 interrupts = <170 IRQ_TYPE_LEVEL_HIGH>, 273 <171 IRQ_TYPE_LEVEL_HIGH>, 274 <172 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&rootclk PB2CLK>; 276 status = "disabled"; 277 }; 278 279 uart5: serial@1f822800 { 280 compatible = "microchip,pic32mzda-uart"; 281 reg = <0x1f822800 0x50>; 282 interrupts = <179 IRQ_TYPE_LEVEL_HIGH>, 283 <180 IRQ_TYPE_LEVEL_HIGH>, 284 <181 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&rootclk PB2CLK>; 286 status = "disabled"; 287 }; 288 289 uart6: serial@1f822A00 { 290 compatible = "microchip,pic32mzda-uart"; 291 reg = <0x1f822A00 0x50>; 292 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>, 293 <189 IRQ_TYPE_LEVEL_HIGH>, 294 <190 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&rootclk PB2CLK>; 296 status = "disabled"; 297 }; 298}; 299