1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 3#include <dt-bindings/clock/ingenic,tcu.h> 4 5/ { 6 #address-cells = <1>; 7 #size-cells = <1>; 8 compatible = "ingenic,jz4725b"; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu0: cpu@0 { 15 device_type = "cpu"; 16 compatible = "ingenic,xburst-mxu1.0"; 17 reg = <0>; 18 19 clocks = <&cgu JZ4725B_CLK_CCLK>; 20 clock-names = "cpu"; 21 }; 22 }; 23 24 cpuintc: interrupt-controller { 25 #address-cells = <0>; 26 #interrupt-cells = <1>; 27 interrupt-controller; 28 compatible = "mti,cpu-interrupt-controller"; 29 }; 30 31 intc: interrupt-controller@10001000 { 32 compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc"; 33 reg = <0x10001000 0x14>; 34 35 interrupt-controller; 36 #interrupt-cells = <1>; 37 38 interrupt-parent = <&cpuintc>; 39 interrupts = <2>; 40 }; 41 42 ext: ext { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 }; 46 47 osc32k: osc32k { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <32768>; 51 }; 52 53 cgu: clock-controller@10000000 { 54 compatible = "ingenic,jz4725b-cgu"; 55 reg = <0x10000000 0x100>; 56 57 clocks = <&ext>, <&osc32k>; 58 clock-names = "ext", "osc32k"; 59 60 #clock-cells = <1>; 61 }; 62 63 tcu: timer@10002000 { 64 compatible = "ingenic,jz4725b-tcu", "simple-mfd"; 65 reg = <0x10002000 0x1000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0x0 0x10002000 0x1000>; 69 70 #clock-cells = <1>; 71 72 clocks = <&cgu JZ4725B_CLK_RTC>, 73 <&cgu JZ4725B_CLK_EXT>, 74 <&cgu JZ4725B_CLK_PCLK>, 75 <&cgu JZ4725B_CLK_TCU>; 76 clock-names = "rtc", "ext", "pclk", "tcu"; 77 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 81 interrupt-parent = <&intc>; 82 interrupts = <23>, <22>, <21>; 83 84 watchdog: watchdog@0 { 85 compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog"; 86 reg = <0x0 0xc>; 87 88 clocks = <&tcu TCU_CLK_WDT>; 89 clock-names = "wdt"; 90 }; 91 92 pwm: pwm@60 { 93 compatible = "ingenic,jz4725b-pwm"; 94 reg = <0x60 0x40>; 95 96 #pwm-cells = <3>; 97 98 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, 99 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, 100 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>; 101 clock-names = "timer0", "timer1", "timer2", 102 "timer3", "timer4", "timer5"; 103 }; 104 105 ost: timer@e0 { 106 compatible = "ingenic,jz4725b-ost"; 107 reg = <0xe0 0x20>; 108 109 clocks = <&tcu TCU_CLK_OST>; 110 clock-names = "ost"; 111 112 interrupts = <15>; 113 }; 114 }; 115 116 rtc_dev: rtc@10003000 { 117 compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc"; 118 reg = <0x10003000 0x40>; 119 120 interrupt-parent = <&intc>; 121 interrupts = <6>; 122 123 clocks = <&cgu JZ4725B_CLK_RTC>; 124 clock-names = "rtc"; 125 }; 126 127 pinctrl: pinctrl@10010000 { 128 compatible = "ingenic,jz4725b-pinctrl"; 129 reg = <0x10010000 0x400>; 130 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 gpa: gpio@0 { 135 compatible = "ingenic,jz4725b-gpio"; 136 reg = <0>; 137 138 gpio-controller; 139 gpio-ranges = <&pinctrl 0 0 32>; 140 #gpio-cells = <2>; 141 142 interrupt-controller; 143 #interrupt-cells = <2>; 144 145 interrupt-parent = <&intc>; 146 interrupts = <16>; 147 }; 148 149 gpb: gpio@1 { 150 compatible = "ingenic,jz4725b-gpio"; 151 reg = <1>; 152 153 gpio-controller; 154 gpio-ranges = <&pinctrl 0 32 32>; 155 #gpio-cells = <2>; 156 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 160 interrupt-parent = <&intc>; 161 interrupts = <15>; 162 }; 163 164 gpc: gpio@2 { 165 compatible = "ingenic,jz4725b-gpio"; 166 reg = <2>; 167 168 gpio-controller; 169 gpio-ranges = <&pinctrl 0 64 32>; 170 #gpio-cells = <2>; 171 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 175 interrupt-parent = <&intc>; 176 interrupts = <14>; 177 }; 178 179 gpd: gpio@3 { 180 compatible = "ingenic,jz4725b-gpio"; 181 reg = <3>; 182 183 gpio-controller; 184 gpio-ranges = <&pinctrl 0 96 32>; 185 #gpio-cells = <2>; 186 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 190 interrupt-parent = <&intc>; 191 interrupts = <13>; 192 }; 193 }; 194 195 aic: audio-controller@10020000 { 196 compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s"; 197 reg = <0x10020000 0x38>; 198 199 #sound-dai-cells = <0>; 200 201 clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>; 202 clock-names = "aic", "i2s"; 203 204 interrupt-parent = <&intc>; 205 interrupts = <10>; 206 207 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; 208 dma-names = "rx", "tx"; 209 }; 210 211 codec: audio-codec@100200a4 { 212 compatible = "ingenic,jz4725b-codec"; 213 reg = <0x100200a4 0x8>; 214 215 #sound-dai-cells = <0>; 216 217 clocks = <&cgu JZ4725B_CLK_AIC>; 218 clock-names = "aic"; 219 }; 220 221 mmc0: mmc@10021000 { 222 compatible = "ingenic,jz4725b-mmc"; 223 reg = <0x10021000 0x1000>; 224 225 clocks = <&cgu JZ4725B_CLK_MMC0>; 226 clock-names = "mmc"; 227 228 interrupt-parent = <&intc>; 229 interrupts = <25>; 230 231 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>; 232 dma-names = "rx", "tx"; 233 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 cap-sdio-irq; 237 }; 238 239 mmc1: mmc@10022000 { 240 compatible = "ingenic,jz4725b-mmc"; 241 reg = <0x10022000 0x1000>; 242 243 clocks = <&cgu JZ4725B_CLK_MMC1>; 244 clock-names = "mmc"; 245 246 interrupt-parent = <&intc>; 247 interrupts = <24>; 248 249 dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>; 250 dma-names = "rx", "tx"; 251 252 cap-sd-highspeed; 253 cap-mmc-highspeed; 254 cap-sdio-irq; 255 }; 256 257 uart: serial@10030000 { 258 compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart"; 259 reg = <0x10030000 0x100>; 260 261 interrupt-parent = <&intc>; 262 interrupts = <9>; 263 264 clocks = <&ext>, <&cgu JZ4725B_CLK_UART>; 265 clock-names = "baud", "module"; 266 }; 267 268 adc: adc@10070000 { 269 compatible = "ingenic,jz4725b-adc"; 270 #io-channel-cells = <1>; 271 272 reg = <0x10070000 0x30>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 ranges = <0x0 0x10070000 0x30>; 276 277 clocks = <&cgu JZ4725B_CLK_ADC>; 278 clock-names = "adc"; 279 280 interrupt-parent = <&intc>; 281 interrupts = <18>; 282 }; 283 284 nemc: memory-controller@13010000 { 285 compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc"; 286 reg = <0x13010000 0x10000>; 287 #address-cells = <2>; 288 #size-cells = <1>; 289 ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>, 290 <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>; 291 292 clocks = <&cgu JZ4725B_CLK_MCLK>; 293 }; 294 295 dmac: dma-controller@13020000 { 296 compatible = "ingenic,jz4725b-dma"; 297 reg = <0x13020000 0xd8>, <0x13020300 0x14>; 298 299 #dma-cells = <2>; 300 301 interrupt-parent = <&intc>; 302 interrupts = <29>; 303 304 clocks = <&cgu JZ4725B_CLK_DMA>; 305 }; 306 307 udc: usb@13040000 { 308 compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb"; 309 reg = <0x13040000 0x10000>; 310 311 interrupt-parent = <&intc>; 312 interrupts = <27>; 313 interrupt-names = "mc"; 314 315 clocks = <&cgu JZ4725B_CLK_UDC>; 316 clock-names = "udc"; 317 }; 318 319 lcd: lcd-controller@13050000 { 320 compatible = "ingenic,jz4725b-lcd"; 321 reg = <0x13050000 0x130>; /* tbc */ 322 323 interrupt-parent = <&intc>; 324 interrupts = <31>; 325 326 clocks = <&cgu JZ4725B_CLK_LCD>; 327 clock-names = "lcd_pclk"; 328 329 lcd_ports: ports { 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 port@8 { 334 reg = <8>; 335 336 ipu_output: endpoint { 337 remote-endpoint = <&ipu_input>; 338 }; 339 }; 340 }; 341 }; 342 343 ipu: ipu@13080000 { 344 compatible = "ingenic,jz4725b-ipu"; 345 reg = <0x13080000 0x64>; 346 347 interrupt-parent = <&intc>; 348 interrupts = <30>; 349 350 clocks = <&cgu JZ4725B_CLK_IPU>; 351 clock-names = "ipu"; 352 353 port { 354 ipu_input: endpoint { 355 remote-endpoint = <&ipu_output>; 356 }; 357 }; 358 }; 359 360 bch: ecc-controller@130d0000 { 361 compatible = "ingenic,jz4725b-bch"; 362 reg = <0x130d0000 0x44>; 363 364 clocks = <&cgu JZ4725B_CLK_BCH>; 365 }; 366 367 rom: memory@1fc00000 { 368 compatible = "mtd-rom"; 369 probe-type = "map_rom"; 370 reg = <0x1fc00000 0x2000>; 371 372 bank-width = <4>; 373 device-width = <1>; 374 }; 375}; 376