1// SPDX-License-Identifier: GPL-2.0 2 3#include "dt-bindings/clock/bcm6362-clock.h" 4#include "dt-bindings/reset/bcm6362-reset.h" 5#include "dt-bindings/soc/bcm6362-pm.h" 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "brcm,bcm6362"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 mips-hpt-frequency = <200000000>; 17 18 cpu@0 { 19 compatible = "brcm,bmips4350"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 24 cpu@1 { 25 compatible = "brcm,bmips4350"; 26 device_type = "cpu"; 27 reg = <1>; 28 }; 29 }; 30 31 clocks { 32 periph_osc: periph-osc { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <50000000>; 36 clock-output-names = "periph"; 37 }; 38 39 hsspi_osc: hsspi-osc { 40 compatible = "fixed-clock"; 41 42 #clock-cells = <0>; 43 44 clock-frequency = <400000000>; 45 clock-output-names = "hsspi_osc"; 46 }; 47 }; 48 49 aliases { 50 nflash = &nflash; 51 serial0 = &uart0; 52 serial1 = &uart1; 53 spi0 = &lsspi; 54 spi1 = &hsspi; 55 }; 56 57 cpu_intc: interrupt-controller { 58 #address-cells = <0>; 59 compatible = "mti,cpu-interrupt-controller"; 60 61 interrupt-controller; 62 #interrupt-cells = <1>; 63 }; 64 65 ubus { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 compatible = "simple-bus"; 70 ranges; 71 72 periph_clk: clock-controller@10000004 { 73 compatible = "brcm,bcm6362-clocks"; 74 reg = <0x10000004 0x4>; 75 #clock-cells = <1>; 76 }; 77 78 pll_cntl: syscon@10000008 { 79 compatible = "syscon"; 80 reg = <0x10000008 0x4>; 81 native-endian; 82 83 reboot { 84 compatible = "syscon-reboot"; 85 offset = <0x0>; 86 mask = <0x1>; 87 }; 88 }; 89 90 periph_rst: reset-controller@10000010 { 91 compatible = "brcm,bcm6345-reset"; 92 reg = <0x10000010 0x4>; 93 #reset-cells = <1>; 94 }; 95 96 periph_intc: interrupt-controller@10000020 { 97 compatible = "brcm,bcm6345-l1-intc"; 98 reg = <0x10000020 0x10>, 99 <0x10000030 0x10>; 100 101 interrupt-controller; 102 #interrupt-cells = <1>; 103 104 interrupt-parent = <&cpu_intc>; 105 interrupts = <2>, <3>; 106 }; 107 108 wdt: watchdog@1000005c { 109 compatible = "brcm,bcm7038-wdt"; 110 reg = <0x1000005c 0xc>; 111 112 clocks = <&periph_osc>; 113 clock-names = "refclk"; 114 115 timeout-sec = <30>; 116 }; 117 118 uart0: serial@10000100 { 119 compatible = "brcm,bcm6345-uart"; 120 reg = <0x10000100 0x18>; 121 122 interrupt-parent = <&periph_intc>; 123 interrupts = <3>; 124 125 clocks = <&periph_osc>; 126 clock-names = "refclk"; 127 128 status = "disabled"; 129 }; 130 131 uart1: serial@10000120 { 132 compatible = "brcm,bcm6345-uart"; 133 reg = <0x10000120 0x18>; 134 135 interrupt-parent = <&periph_intc>; 136 interrupts = <4>; 137 138 clocks = <&periph_osc>; 139 clock-names = "refclk"; 140 141 status = "disabled"; 142 }; 143 144 nflash: nand@10000200 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 compatible = "brcm,nand-bcm6368", 148 "brcm,brcmnand-v2.2", 149 "brcm,brcmnand"; 150 reg = <0x10000200 0x180>, 151 <0x10000600 0x200>, 152 <0x10000070 0x10>; 153 reg-names = "nand", 154 "nand-cache", 155 "nand-int-base"; 156 157 interrupt-parent = <&periph_intc>; 158 interrupts = <12>; 159 160 clocks = <&periph_clk BCM6362_CLK_NAND>; 161 clock-names = "nand"; 162 163 status = "disabled"; 164 }; 165 166 lsspi: spi@10000800 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "brcm,bcm6358-spi"; 170 reg = <0x10000800 0x70c>; 171 172 interrupt-parent = <&periph_intc>; 173 interrupts = <2>; 174 175 clocks = <&periph_clk BCM6362_CLK_SPI>; 176 clock-names = "spi"; 177 178 resets = <&periph_rst BCM6362_RST_SPI>; 179 reset-names = "spi"; 180 181 status = "disabled"; 182 }; 183 184 hsspi: spi@10001000 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "brcm,bcm6328-hsspi"; 188 reg = <0x10001000 0x600>; 189 190 interrupt-parent = <&periph_intc>; 191 interrupts = <5>; 192 193 clocks = <&periph_clk BCM6362_CLK_HSSPI>, 194 <&hsspi_osc>; 195 clock-names = "hsspi", 196 "pll"; 197 198 resets = <&periph_rst BCM6362_RST_SPI>; 199 reset-names = "hsspi"; 200 201 status = "disabled"; 202 }; 203 204 periph_pwr: power-controller@10001848 { 205 compatible = "brcm,bcm6362-power-controller"; 206 reg = <0x10001848 0x4>; 207 #power-domain-cells = <1>; 208 }; 209 210 leds0: led-controller@10001900 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "brcm,bcm6328-leds"; 214 reg = <0x10001900 0x24>; 215 216 status = "disabled"; 217 }; 218 219 ehci: usb@10002500 { 220 compatible = "brcm,bcm6362-ehci", "generic-ehci"; 221 reg = <0x10002500 0x100>; 222 big-endian; 223 224 interrupt-parent = <&periph_intc>; 225 interrupts = <10>; 226 227 phys = <&usbh 0>; 228 phy-names = "usb"; 229 230 status = "disabled"; 231 }; 232 233 ohci: usb@10002600 { 234 compatible = "brcm,bcm6362-ohci", "generic-ohci"; 235 reg = <0x10002600 0x100>; 236 big-endian; 237 no-big-frame-no; 238 239 interrupt-parent = <&periph_intc>; 240 interrupts = <9>; 241 242 phys = <&usbh 0>; 243 phy-names = "usb"; 244 245 status = "disabled"; 246 }; 247 248 usbh: usb-phy@10002700 { 249 compatible = "brcm,bcm6362-usbh-phy"; 250 reg = <0x10002700 0x38>; 251 252 #phy-cells = <1>; 253 254 clocks = <&periph_clk BCM6362_CLK_USBH>; 255 clock-names = "usbh"; 256 257 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>; 258 259 resets = <&periph_rst BCM6362_RST_USBH>; 260 reset-names = "usbh"; 261 262 status = "disabled"; 263 }; 264 }; 265}; 266