1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Loongson Technology Corporation Limited 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@1 { 19 compatible = "loongson,la364"; 20 device_type = "cpu"; 21 reg = <0x0>; 22 clocks = <&cpu_clk>; 23 }; 24 25 cpu1: cpu@2 { 26 compatible = "loongson,la364"; 27 device_type = "cpu"; 28 reg = <0x1>; 29 clocks = <&cpu_clk>; 30 }; 31 }; 32 33 cpu_clk: cpu-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <1400000000>; 37 }; 38 39 cpuintc: interrupt-controller { 40 compatible = "loongson,cpu-interrupt-controller"; 41 #interrupt-cells = <1>; 42 interrupt-controller; 43 }; 44 45 bus@10000000 { 46 compatible = "simple-bus"; 47 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 48 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 49 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 50 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 54 pmc: power-management@100d0000 { 55 compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon"; 56 reg = <0x0 0x100d0000 0x0 0x58>; 57 interrupt-parent = <&eiointc>; 58 interrupts = <47>; 59 loongson,suspend-address = <0x0 0x1c000500>; 60 61 syscon-reboot { 62 compatible = "syscon-reboot"; 63 offset = <0x30>; 64 mask = <0x1>; 65 }; 66 67 syscon-poweroff { 68 compatible = "syscon-poweroff"; 69 regmap = <&pmc>; 70 offset = <0x14>; 71 mask = <0x3c00>; 72 value = <0x3c00>; 73 }; 74 }; 75 76 liointc: interrupt-controller@1fe01400 { 77 compatible = "loongson,liointc-1.0"; 78 reg = <0x0 0x1fe01400 0x0 0x64>; 79 80 interrupt-controller; 81 #interrupt-cells = <2>; 82 interrupt-parent = <&cpuintc>; 83 interrupts = <2>; 84 interrupt-names = "int0"; 85 loongson,parent_int_map = <0xffffffff>, /* int0 */ 86 <0x00000000>, /* int1 */ 87 <0x00000000>, /* int2 */ 88 <0x00000000>; /* int3 */ 89 }; 90 91 eiointc: interrupt-controller@1fe01600 { 92 compatible = "loongson,ls2k2000-eiointc"; 93 reg = <0x0 0x1fe01600 0x0 0xea00>; 94 interrupt-controller; 95 #interrupt-cells = <1>; 96 interrupt-parent = <&cpuintc>; 97 interrupts = <3>; 98 }; 99 100 pic: interrupt-controller@10000000 { 101 compatible = "loongson,pch-pic-1.0"; 102 reg = <0x0 0x10000000 0x0 0x400>; 103 interrupt-controller; 104 #interrupt-cells = <2>; 105 loongson,pic-base-vec = <0>; 106 interrupt-parent = <&eiointc>; 107 }; 108 109 msi: msi-controller@1fe01140 { 110 compatible = "loongson,pch-msi-1.0"; 111 reg = <0x0 0x1fe01140 0x0 0x8>; 112 msi-controller; 113 loongson,msi-base-vec = <64>; 114 loongson,msi-num-vecs = <192>; 115 interrupt-parent = <&eiointc>; 116 }; 117 118 rtc0: rtc@100d0100 { 119 compatible = "loongson,ls2k2000-rtc", "loongson,ls7a-rtc"; 120 reg = <0x0 0x100d0100 0x0 0x100>; 121 interrupt-parent = <&pic>; 122 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; 123 status = "disabled"; 124 }; 125 126 uart0: serial@1fe001e0 { 127 compatible = "ns16550a"; 128 reg = <0x0 0x1fe001e0 0x0 0x10>; 129 clock-frequency = <100000000>; 130 interrupt-parent = <&liointc>; 131 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 132 no-loopback-test; 133 status = "disabled"; 134 }; 135 136 pcie@1a000000 { 137 compatible = "loongson,ls2k-pci"; 138 reg = <0x0 0x1a000000 0x0 0x02000000>, 139 <0xfe 0x0 0x0 0x20000000>; 140 #address-cells = <3>; 141 #size-cells = <2>; 142 device_type = "pci"; 143 bus-range = <0x0 0xff>; 144 ranges = <0x01000000 0x0 0x00008000 0x0 0x18400000 0x0 0x00008000>, 145 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 146 147 gmac0: ethernet@3,0 { 148 reg = <0x1800 0x0 0x0 0x0 0x0>; 149 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 150 interrupt-parent = <&pic>; 151 status = "disabled"; 152 }; 153 154 gmac1: ethernet@3,1 { 155 reg = <0x1900 0x0 0x0 0x0 0x0>; 156 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-parent = <&pic>; 158 status = "disabled"; 159 }; 160 161 gmac2: ethernet@3,2 { 162 reg = <0x1a00 0x0 0x0 0x0 0x0>; 163 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-parent = <&pic>; 165 status = "disabled"; 166 }; 167 168 xhci0: usb@4,0 { 169 reg = <0x2000 0x0 0x0 0x0 0x0>; 170 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-parent = <&pic>; 172 status = "disabled"; 173 }; 174 175 xhci1: usb@19,0 { 176 reg = <0xc800 0x0 0x0 0x0 0x0>; 177 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-parent = <&pic>; 179 status = "disabled"; 180 }; 181 182 display@6,1 { 183 reg = <0x3100 0x0 0x0 0x0 0x0>; 184 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-parent = <&pic>; 186 status = "disabled"; 187 }; 188 189 hda@7,0 { 190 reg = <0x3800 0x0 0x0 0x0 0x0>; 191 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-parent = <&pic>; 193 status = "disabled"; 194 }; 195 196 sata: sata@8,0 { 197 reg = <0x4000 0x0 0x0 0x0 0x0>; 198 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-parent = <&pic>; 200 status = "disabled"; 201 }; 202 203 pcie@9,0 { 204 reg = <0x4800 0x0 0x0 0x0 0x0>; 205 #address-cells = <3>; 206 #size-cells = <2>; 207 device_type = "pci"; 208 interrupt-parent = <&pic>; 209 #interrupt-cells = <1>; 210 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 211 interrupt-map = <0x0 0x0 0x0 0x0 &pic 32 IRQ_TYPE_LEVEL_HIGH>; 212 ranges; 213 }; 214 215 pcie@a,0 { 216 reg = <0x5000 0x0 0x0 0x0 0x0>; 217 #address-cells = <3>; 218 #size-cells = <2>; 219 device_type = "pci"; 220 interrupt-parent = <&pic>; 221 #interrupt-cells = <1>; 222 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 223 interrupt-map = <0x0 0x0 0x0 0x0 &pic 33 IRQ_TYPE_LEVEL_HIGH>; 224 ranges; 225 }; 226 227 pcie@b,0 { 228 reg = <0x5800 0x0 0x0 0x0 0x0>; 229 #address-cells = <3>; 230 #size-cells = <2>; 231 device_type = "pci"; 232 interrupt-parent = <&pic>; 233 #interrupt-cells = <1>; 234 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 235 interrupt-map = <0x0 0x0 0x0 0x0 &pic 34 IRQ_TYPE_LEVEL_HIGH>; 236 ranges; 237 }; 238 239 pcie@c,0 { 240 reg = <0x6000 0x0 0x0 0x0 0x0>; 241 #address-cells = <3>; 242 #size-cells = <2>; 243 device_type = "pci"; 244 interrupt-parent = <&pic>; 245 #interrupt-cells = <1>; 246 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 247 interrupt-map = <0x0 0x0 0x0 0x0 &pic 35 IRQ_TYPE_LEVEL_HIGH>; 248 ranges; 249 }; 250 251 pcie@d,0 { 252 reg = <0x6800 0x0 0x0 0x0 0x0>; 253 #address-cells = <3>; 254 #size-cells = <2>; 255 device_type = "pci"; 256 interrupt-parent = <&pic>; 257 #interrupt-cells = <1>; 258 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 259 interrupt-map = <0x0 0x0 0x0 0x0 &pic 36 IRQ_TYPE_LEVEL_HIGH>; 260 ranges; 261 }; 262 263 pcie@e,0 { 264 reg = <0x7000 0x0 0x0 0x0 0x0>; 265 #address-cells = <3>; 266 #size-cells = <2>; 267 device_type = "pci"; 268 interrupt-parent = <&pic>; 269 #interrupt-cells = <1>; 270 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 271 interrupt-map = <0x0 0x0 0x0 0x0 &pic 37 IRQ_TYPE_LEVEL_HIGH>; 272 ranges; 273 }; 274 275 pcie@f,0 { 276 reg = <0x7800 0x0 0x0 0x0 0x0>; 277 #address-cells = <3>; 278 #size-cells = <2>; 279 device_type = "pci"; 280 interrupt-parent = <&pic>; 281 #interrupt-cells = <1>; 282 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 283 interrupt-map = <0x0 0x0 0x0 0x0 &pic 40 IRQ_TYPE_LEVEL_HIGH>; 284 ranges; 285 }; 286 287 pcie@10,0 { 288 reg = <0x8000 0x0 0x0 0x0 0x0>; 289 #address-cells = <3>; 290 #size-cells = <2>; 291 device_type = "pci"; 292 interrupt-parent = <&pic>; 293 #interrupt-cells = <1>; 294 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 295 interrupt-map = <0x0 0x0 0x0 0x0 &pic 30 IRQ_TYPE_LEVEL_HIGH>; 296 ranges; 297 }; 298 }; 299 }; 300}; 301