1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Loongson Technology Corporation Limited 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/clock/loongson,ls2k-clk.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "loongson,la264"; 22 device_type = "cpu"; 23 reg= <0x0>; 24 clocks = <&clk LOONGSON2_NODE_CLK>; 25 }; 26 27 cpu1: cpu@1 { 28 compatible = "loongson,la264"; 29 device_type = "cpu"; 30 reg = <0x1>; 31 clocks = <&clk LOONGSON2_NODE_CLK>; 32 }; 33 }; 34 35 ref_100m: clock-ref-100m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <100000000>; 39 clock-output-names = "ref_100m"; 40 }; 41 42 cpuintc: interrupt-controller { 43 compatible = "loongson,cpu-interrupt-controller"; 44 #interrupt-cells = <1>; 45 interrupt-controller; 46 }; 47 48 /* i2c of the dvi eeprom edid */ 49 i2c-gpio-0 { 50 compatible = "i2c-gpio"; 51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 52 sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 53 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 54 #address-cells = <1>; 55 #size-cells = <0>; 56 status = "disabled"; 57 }; 58 59 /* i2c of the eeprom edid */ 60 i2c-gpio-1 { 61 compatible = "i2c-gpio"; 62 scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 63 sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 65 #address-cells = <1>; 66 #size-cells = <0>; 67 status = "disabled"; 68 }; 69 70 thermal-zones { 71 cpu-thermal { 72 polling-delay-passive = <1000>; 73 polling-delay = <5000>; 74 thermal-sensors = <&tsensor 0>; 75 76 trips { 77 cpu_alert: cpu-alert { 78 temperature = <33000>; 79 hysteresis = <2000>; 80 type = "active"; 81 }; 82 83 cpu_crit: cpu-crit { 84 temperature = <85000>; 85 hysteresis = <5000>; 86 type = "critical"; 87 }; 88 }; 89 }; 90 }; 91 92 bus@10000000 { 93 compatible = "simple-bus"; 94 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 95 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 96 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>, 97 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 98 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 99 #address-cells = <2>; 100 #size-cells = <2>; 101 dma-coherent; 102 103 liointc0: interrupt-controller@1fe01400 { 104 compatible = "loongson,liointc-2.0"; 105 reg = <0x0 0x1fe01400 0x0 0x40>, 106 <0x0 0x1fe01040 0x0 0x8>, 107 <0x0 0x1fe01140 0x0 0x8>; 108 reg-names = "main", "isr0", "isr1"; 109 interrupt-controller; 110 #interrupt-cells = <2>; 111 interrupt-parent = <&cpuintc>; 112 interrupts = <2>; 113 interrupt-names = "int0"; 114 loongson,parent_int_map = <0xffffffff>, /* int0 */ 115 <0x00000000>, /* int1 */ 116 <0x00000000>, /* int2 */ 117 <0x00000000>; /* int3 */ 118 }; 119 120 liointc1: interrupt-controller@1fe01440 { 121 compatible = "loongson,liointc-2.0"; 122 reg = <0x0 0x1fe01440 0x0 0x40>, 123 <0x0 0x1fe01048 0x0 0x8>, 124 <0x0 0x1fe01148 0x0 0x8>; 125 reg-names = "main", "isr0", "isr1"; 126 interrupt-controller; 127 #interrupt-cells = <2>; 128 interrupt-parent = <&cpuintc>; 129 interrupts = <3>; 130 interrupt-names = "int1"; 131 loongson,parent_int_map = <0x00000000>, /* int0 */ 132 <0xffffffff>, /* int1 */ 133 <0x00000000>, /* int2 */ 134 <0x00000000>; /* int3 */ 135 }; 136 137 chipid@1fe00000 { 138 compatible = "loongson,ls2k-chipid"; 139 reg = <0x0 0x1fe00000 0x0 0x30>; 140 little-endian; 141 }; 142 143 pctrl: pinctrl@1fe00420 { 144 compatible = "loongson,ls2k-pinctrl"; 145 reg = <0x0 0x1fe00420 0x0 0x18>; 146 status = "disabled"; 147 }; 148 149 clk: clock-controller@1fe00480 { 150 compatible = "loongson,ls2k-clk"; 151 reg = <0x0 0x1fe00480 0x0 0x58>; 152 #clock-cells = <1>; 153 clocks = <&ref_100m>; 154 clock-names = "ref_100m"; 155 status = "disabled"; 156 }; 157 158 gpio0: gpio@1fe00500 { 159 compatible = "loongson,ls2k-gpio"; 160 reg = <0x0 0x1fe00500 0x0 0x38>; 161 ngpios = <64>; 162 #gpio-cells = <2>; 163 gpio-controller; 164 gpio-ranges = <&pctrl 0x0 0x0 15>, 165 <&pctrl 16 16 15>, 166 <&pctrl 32 32 10>, 167 <&pctrl 44 44 20>; 168 interrupt-parent = <&liointc1>; 169 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>, 170 <29 IRQ_TYPE_LEVEL_HIGH>, 171 <30 IRQ_TYPE_LEVEL_HIGH>, 172 <30 IRQ_TYPE_LEVEL_HIGH>, 173 <26 IRQ_TYPE_LEVEL_HIGH>, 174 <26 IRQ_TYPE_LEVEL_HIGH>, 175 <26 IRQ_TYPE_LEVEL_HIGH>, 176 <26 IRQ_TYPE_LEVEL_HIGH>, 177 <26 IRQ_TYPE_LEVEL_HIGH>, 178 <26 IRQ_TYPE_LEVEL_HIGH>, 179 <26 IRQ_TYPE_LEVEL_HIGH>, 180 <26 IRQ_TYPE_LEVEL_HIGH>, 181 <26 IRQ_TYPE_LEVEL_HIGH>, 182 <26 IRQ_TYPE_LEVEL_HIGH>, 183 <26 IRQ_TYPE_LEVEL_HIGH>, 184 <>, 185 <26 IRQ_TYPE_LEVEL_HIGH>, 186 <26 IRQ_TYPE_LEVEL_HIGH>, 187 <26 IRQ_TYPE_LEVEL_HIGH>, 188 <26 IRQ_TYPE_LEVEL_HIGH>, 189 <26 IRQ_TYPE_LEVEL_HIGH>, 190 <26 IRQ_TYPE_LEVEL_HIGH>, 191 <26 IRQ_TYPE_LEVEL_HIGH>, 192 <26 IRQ_TYPE_LEVEL_HIGH>, 193 <26 IRQ_TYPE_LEVEL_HIGH>, 194 <26 IRQ_TYPE_LEVEL_HIGH>, 195 <26 IRQ_TYPE_LEVEL_HIGH>, 196 <26 IRQ_TYPE_LEVEL_HIGH>, 197 <26 IRQ_TYPE_LEVEL_HIGH>, 198 <26 IRQ_TYPE_LEVEL_HIGH>, 199 <26 IRQ_TYPE_LEVEL_HIGH>, 200 <26 IRQ_TYPE_LEVEL_HIGH>, 201 <27 IRQ_TYPE_LEVEL_HIGH>, 202 <27 IRQ_TYPE_LEVEL_HIGH>, 203 <27 IRQ_TYPE_LEVEL_HIGH>, 204 <27 IRQ_TYPE_LEVEL_HIGH>, 205 <27 IRQ_TYPE_LEVEL_HIGH>, 206 <>, 207 <27 IRQ_TYPE_LEVEL_HIGH>, 208 <27 IRQ_TYPE_LEVEL_HIGH>, 209 <27 IRQ_TYPE_LEVEL_HIGH>, 210 <27 IRQ_TYPE_LEVEL_HIGH>, 211 <>, 212 <>, 213 <27 IRQ_TYPE_LEVEL_HIGH>, 214 <27 IRQ_TYPE_LEVEL_HIGH>, 215 <27 IRQ_TYPE_LEVEL_HIGH>, 216 <27 IRQ_TYPE_LEVEL_HIGH>, 217 <27 IRQ_TYPE_LEVEL_HIGH>, 218 <27 IRQ_TYPE_LEVEL_HIGH>, 219 <27 IRQ_TYPE_LEVEL_HIGH>, 220 <27 IRQ_TYPE_LEVEL_HIGH>, 221 <27 IRQ_TYPE_LEVEL_HIGH>, 222 <27 IRQ_TYPE_LEVEL_HIGH>, 223 <27 IRQ_TYPE_LEVEL_HIGH>, 224 <27 IRQ_TYPE_LEVEL_HIGH>, 225 <27 IRQ_TYPE_LEVEL_HIGH>, 226 <27 IRQ_TYPE_LEVEL_HIGH>, 227 <27 IRQ_TYPE_LEVEL_HIGH>, 228 <27 IRQ_TYPE_LEVEL_HIGH>, 229 <27 IRQ_TYPE_LEVEL_HIGH>, 230 <27 IRQ_TYPE_LEVEL_HIGH>, 231 <27 IRQ_TYPE_LEVEL_HIGH>, 232 <27 IRQ_TYPE_LEVEL_HIGH>; 233 }; 234 235 tsensor: thermal-sensor@1fe01500 { 236 compatible = "loongson,ls2k1000-thermal"; 237 reg = <0x0 0x1fe01500 0x0 0x30>; 238 interrupt-parent = <&liointc0>; 239 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 240 #thermal-sensor-cells = <1>; 241 }; 242 243 dma-controller@1fe00c00 { 244 compatible = "loongson,ls2k1000-apbdma"; 245 reg = <0x0 0x1fe00c00 0x0 0x8>; 246 interrupt-parent = <&liointc1>; 247 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clk LOONGSON2_APB_CLK>; 249 #dma-cells = <1>; 250 status = "disabled"; 251 }; 252 253 dma-controller@1fe00c10 { 254 compatible = "loongson,ls2k1000-apbdma"; 255 reg = <0x0 0x1fe00c10 0x0 0x8>; 256 interrupt-parent = <&liointc1>; 257 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&clk LOONGSON2_APB_CLK>; 259 #dma-cells = <1>; 260 status = "disabled"; 261 }; 262 263 dma-controller@1fe00c20 { 264 compatible = "loongson,ls2k1000-apbdma"; 265 reg = <0x0 0x1fe00c20 0x0 0x8>; 266 interrupt-parent = <&liointc1>; 267 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clk LOONGSON2_APB_CLK>; 269 #dma-cells = <1>; 270 status = "disabled"; 271 }; 272 273 dma-controller@1fe00c30 { 274 compatible = "loongson,ls2k1000-apbdma"; 275 reg = <0x0 0x1fe00c30 0x0 0x8>; 276 interrupt-parent = <&liointc1>; 277 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&clk LOONGSON2_APB_CLK>; 279 #dma-cells = <1>; 280 status = "disabled"; 281 }; 282 283 dma-controller@1fe00c40 { 284 compatible = "loongson,ls2k1000-apbdma"; 285 reg = <0x0 0x1fe00c40 0x0 0x8>; 286 interrupt-parent = <&liointc1>; 287 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clk LOONGSON2_APB_CLK>; 289 #dma-cells = <1>; 290 status = "disabled"; 291 }; 292 293 uart0: serial@1fe20000 { 294 compatible = "ns16550a"; 295 reg = <0x0 0x1fe20000 0x0 0x10>; 296 clock-frequency = <125000000>; 297 interrupt-parent = <&liointc0>; 298 interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>; 299 no-loopback-test; 300 status = "disabled"; 301 }; 302 303 i2c2: i2c@1fe21000 { 304 compatible = "loongson,ls2k-i2c"; 305 reg = <0x0 0x1fe21000 0x0 0x8>; 306 interrupt-parent = <&liointc0>; 307 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 308 status = "disabled"; 309 }; 310 311 i2c3: i2c@1fe21800 { 312 compatible = "loongson,ls2k-i2c"; 313 reg = <0x0 0x1fe21800 0x0 0x8>; 314 interrupt-parent = <&liointc0>; 315 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 316 status = "disabled"; 317 }; 318 319 pmc: power-management@1fe27000 { 320 compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon"; 321 reg = <0x0 0x1fe27000 0x0 0x58>; 322 interrupt-parent = <&liointc1>; 323 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 324 loongson,suspend-address = <0x0 0x1c000500>; 325 326 syscon-reboot { 327 compatible = "syscon-reboot"; 328 offset = <0x30>; 329 mask = <0x1>; 330 }; 331 332 syscon-poweroff { 333 compatible = "syscon-poweroff"; 334 regmap = <&pmc>; 335 offset = <0x14>; 336 mask = <0x3c00>; 337 value = <0x3c00>; 338 }; 339 }; 340 341 rtc0: rtc@1fe27800 { 342 compatible = "loongson,ls2k1000-rtc"; 343 reg = <0x0 0x1fe27800 0x0 0x100>; 344 interrupt-parent = <&liointc1>; 345 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 346 status = "disabled"; 347 }; 348 349 spi0: spi@1fff0220 { 350 compatible = "loongson,ls2k1000-spi"; 351 reg = <0x0 0x1fff0220 0x0 0x10>; 352 clocks = <&clk LOONGSON2_BOOT_CLK>; 353 status = "disabled"; 354 }; 355 356 pcie@1a000000 { 357 compatible = "loongson,ls2k-pci"; 358 reg = <0x0 0x1a000000 0x0 0x02000000>, 359 <0xfe 0x0 0x0 0x20000000>; 360 #address-cells = <3>; 361 #size-cells = <2>; 362 device_type = "pci"; 363 bus-range = <0x0 0xff>; 364 ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>, 365 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 366 367 gmac0: ethernet@3,0 { 368 reg = <0x1800 0x0 0x0 0x0 0x0>; 369 interrupt-parent = <&liointc0>; 370 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 371 <13 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-names = "macirq", "eth_lpi"; 373 status = "disabled"; 374 }; 375 376 gmac1: ethernet@3,1 { 377 reg = <0x1900 0x0 0x0 0x0 0x0>; 378 interrupt-parent = <&liointc0>; 379 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 380 <15 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "macirq", "eth_lpi"; 382 status = "disabled"; 383 }; 384 385 ehci0: usb@4,1 { 386 reg = <0x2100 0x0 0x0 0x0 0x0>; 387 interrupt-parent = <&liointc1>; 388 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 389 status = "disabled"; 390 }; 391 392 ohci0: usb@4,2 { 393 reg = <0x2200 0x0 0x0 0x0 0x0>; 394 interrupt-parent = <&liointc1>; 395 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 }; 398 399 display@6,0 { 400 reg = <0x3000 0x0 0x0 0x0 0x0>; 401 interrupt-parent = <&liointc0>; 402 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 403 status = "disabled"; 404 }; 405 406 hda@7,0 { 407 reg = <0x3800 0x0 0x0 0x0 0x0>; 408 interrupt-parent = <&liointc0>; 409 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 410 status = "disabled"; 411 }; 412 413 sata: sata@8,0 { 414 reg = <0x4000 0x0 0x0 0x0 0x0>; 415 interrupt-parent = <&liointc0>; 416 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 417 status = "disabled"; 418 }; 419 420 pcie@9,0 { 421 reg = <0x4800 0x0 0x0 0x0 0x0>; 422 #address-cells = <3>; 423 #size-cells = <2>; 424 device_type = "pci"; 425 #interrupt-cells = <1>; 426 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 427 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>; 428 ranges; 429 }; 430 431 pcie@a,0 { 432 reg = <0x5000 0x0 0x0 0x0 0x0>; 433 #address-cells = <3>; 434 #size-cells = <2>; 435 device_type = "pci"; 436 interrupt-parent = <&liointc1>; 437 #interrupt-cells = <1>; 438 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 439 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; 440 ranges; 441 }; 442 443 pcie@b,0 { 444 reg = <0x5800 0x0 0x0 0x0 0x0>; 445 #address-cells = <3>; 446 #size-cells = <2>; 447 device_type = "pci"; 448 interrupt-parent = <&liointc1>; 449 #interrupt-cells = <1>; 450 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 451 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; 452 ranges; 453 }; 454 455 pcie@c,0 { 456 reg = <0x6000 0x0 0x0 0x0 0x0>; 457 #address-cells = <3>; 458 #size-cells = <2>; 459 device_type = "pci"; 460 interrupt-parent = <&liointc1>; 461 #interrupt-cells = <1>; 462 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 463 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; 464 ranges; 465 }; 466 467 pcie@d,0 { 468 reg = <0x6800 0x0 0x0 0x0 0x0>; 469 #address-cells = <3>; 470 #size-cells = <2>; 471 device_type = "pci"; 472 interrupt-parent = <&liointc1>; 473 #interrupt-cells = <1>; 474 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 475 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; 476 ranges; 477 }; 478 479 pcie@e,0 { 480 reg = <0x7000 0x0 0x0 0x0 0x0>; 481 #address-cells = <3>; 482 #size-cells = <2>; 483 device_type = "pci"; 484 interrupt-parent = <&liointc1>; 485 #interrupt-cells = <1>; 486 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 487 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; 488 ranges; 489 }; 490 }; 491 }; 492}; 493