1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3/ { 4 compatible = "gnu,gdbsim"; 5 #address-cells = <1>; 6 #size-cells = <1>; 7 interrupt-parent = <&h8intc>; 8 9 chosen { 10 bootargs = "earlyprintk=h8300-sim"; 11 stdout-path = <&sci0>; 12 }; 13 aliases { 14 serial0 = &sci0; 15 serial1 = &sci1; 16 }; 17 18 xclk: oscillator { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <33333333>; 22 clock-output-names = "xtal"; 23 }; 24 pllclk: pllclk { 25 compatible = "renesas,h8s2678-pll-clock"; 26 clocks = <&xclk>; 27 #clock-cells = <0>; 28 reg = <0xfee03b 2>, <0xfee045 2>; 29 }; 30 core_clk: core_clk { 31 compatible = "renesas,h8300-div-clock"; 32 clocks = <&pllclk>; 33 #clock-cells = <0>; 34 reg = <0xfee03b 2>; 35 renesas,width = <3>; 36 }; 37 fclk: fclk { 38 compatible = "fixed-factor-clock"; 39 clocks = <&core_clk>; 40 #clock-cells = <0>; 41 clock-div = <1>; 42 clock-mult = <1>; 43 }; 44 45 memory@400000 { 46 device_type = "memory"; 47 reg = <0x400000 0x800000>; 48 }; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 cpu@0 { 54 compatible = "renesas,h8300"; 55 clock-frequency = <33333333>; 56 }; 57 }; 58 59 h8intc: interrupt-controller@fffe00 { 60 compatible = "renesas,h8s-intc", "renesas,h8300-intc"; 61 #interrupt-cells = <2>; 62 interrupt-controller; 63 reg = <0xfffe00 24>; 64 }; 65 66 bsc: memory-controller@fffec0 { 67 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; 68 reg = <0xfffec0 24>; 69 }; 70 71 tpu: timer@ffffe0 { 72 compatible = "renesas,tpu"; 73 reg = <0xffffe0 16>, <0xfffff0 12>; 74 clocks = <&fclk>; 75 clock-names = "fck"; 76 }; 77 78 timer8: timer@ffffb0 { 79 compatible = "renesas,8bit-timer"; 80 reg = <0xffffb0 10>; 81 interrupts = <72 0>; 82 clocks = <&fclk>; 83 clock-names = "fck"; 84 }; 85 86 sci0: serial@ffff78 { 87 compatible = "renesas,sci"; 88 reg = <0xffff78 8>; 89 interrupts = <88 0>, <89 0>, <90 0>, <91 0>; 90 clocks = <&fclk>; 91 clock-names = "fck"; 92 }; 93 sci1: serial@ffff80 { 94 compatible = "renesas,sci"; 95 reg = <0xffff80 8>; 96 interrupts = <92 0>, <93 0>, <94 0>, <95 0>; 97 clocks = <&fclk>; 98 clock-names = "fck"; 99 }; 100}; 101