1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3/ { 4 compatible = "renesas,edosk2674"; 5 #address-cells = <1>; 6 #size-cells = <1>; 7 interrupt-parent = <&h8intc>; 8 9 chosen { 10 bootargs = "console=ttySC2,38400"; 11 stdout-path = &sci2; 12 }; 13 aliases { 14 serial0 = &sci0; 15 serial1 = &sci1; 16 serial2 = &sci2; 17 }; 18 19 xclk: oscillator { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 clock-frequency = <33333333>; 23 clock-output-names = "xtal"; 24 }; 25 pllclk: pllclk { 26 compatible = "renesas,h8s2678-pll-clock"; 27 clocks = <&xclk>; 28 #clock-cells = <0>; 29 reg = <0xffff3b 1>, <0xffff45 1>; 30 }; 31 core_clk: core_clk { 32 compatible = "renesas,h8300-div-clock"; 33 clocks = <&pllclk>; 34 #clock-cells = <0>; 35 reg = <0xffff3b 1>; 36 renesas,width = <3>; 37 }; 38 fclk: fclk { 39 compatible = "fixed-factor-clock"; 40 clocks = <&core_clk>; 41 #clock-cells = <0>; 42 clock-div = <1>; 43 clock-mult = <1>; 44 }; 45 46 memory@400000 { 47 device_type = "memory"; 48 reg = <0x400000 0x800000>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 cpu@0 { 55 compatible = "renesas,h8300"; 56 clock-frequency = <33333333>; 57 }; 58 }; 59 60 h8intc: interrupt-controller@fffe00 { 61 compatible = "renesas,h8s-intc", "renesas,h8300-intc"; 62 #interrupt-cells = <2>; 63 interrupt-controller; 64 reg = <0xfffe00 24>; 65 }; 66 67 bsc: memory-controller@fffec0 { 68 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; 69 reg = <0xfffec0 24>; 70 }; 71 72 tpu: timer@ffffe0 { 73 compatible = "renesas,tpu"; 74 reg = <0xffffe0 16>, <0xfffff0 12>; 75 clocks = <&fclk>; 76 clock-names = "fck"; 77 }; 78 79 timer8: timer@ffffb0 { 80 compatible = "renesas,8bit-timer"; 81 reg = <0xffffb0 10>; 82 interrupts = <72 0>; 83 clocks = <&fclk>; 84 clock-names = "fck"; 85 }; 86 87 sci0: serial@ffff78 { 88 compatible = "renesas,sci"; 89 reg = <0xffff78 8>; 90 interrupts = <88 0>, <89 0>, <90 0>, <91 0>; 91 clocks = <&fclk>; 92 clock-names = "fck"; 93 }; 94 sci1: serial@ffff80 { 95 compatible = "renesas,sci"; 96 reg = <0xffff80 8>; 97 interrupts = <92 0>, <93 0>, <94 0>, <95 0>; 98 clocks = <&fclk>; 99 clock-names = "fck"; 100 }; 101 sci2: serial@ffff88 { 102 compatible = "renesas,sci"; 103 reg = <0xffff88 8>; 104 interrupts = <96 0>, <97 0>, <98 0>, <99 0>; 105 clocks = <&fclk>; 106 clock-names = "fck"; 107 }; 108}; 109