xref: /freebsd/sys/contrib/device-tree/src/arm64/xilinx/zynqmp-zcu104-revA.dts (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU104 RevA";
21	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci1;
27		nvmem0 = &eeprom;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>;
44	};
45
46	clock_8t49n287_5: clk125 {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <125000000>;
50	};
51
52	clock_8t49n287_2: clk26 {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55		clock-frequency = <26000000>;
56	};
57
58	clock_8t49n287_3: clk27 {
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <27000000>;
62	};
63};
64
65&can1 {
66	status = "okay";
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_can1_default>;
69};
70
71&dcc {
72	status = "okay";
73};
74
75&fpd_dma_chan1 {
76	status = "okay";
77};
78
79&fpd_dma_chan2 {
80	status = "okay";
81};
82
83&fpd_dma_chan3 {
84	status = "okay";
85};
86
87&fpd_dma_chan4 {
88	status = "okay";
89};
90
91&fpd_dma_chan5 {
92	status = "okay";
93};
94
95&fpd_dma_chan6 {
96	status = "okay";
97};
98
99&fpd_dma_chan7 {
100	status = "okay";
101};
102
103&fpd_dma_chan8 {
104	status = "okay";
105};
106
107&gem3 {
108	status = "okay";
109	phy-handle = <&phy0>;
110	phy-mode = "rgmii-id";
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_gem3_default>;
113	mdio: mdio {
114		#address-cells = <1>;
115		#size-cells = <0>;
116		phy0: ethernet-phy@c {
117			#phy-cells = <1>;
118			compatible = "ethernet-phy-id2000.a231";
119			reg = <0xc>;
120			ti,rx-internal-delay = <0x8>;
121			ti,tx-internal-delay = <0xa>;
122			ti,fifo-depth = <0x1>;
123			ti,dp83867-rxctrl-strap-quirk;
124			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
125		};
126	};
127};
128
129&gpio {
130	status = "okay";
131};
132
133&gpu {
134	status = "okay";
135};
136
137&i2c1 {
138	status = "okay";
139	clock-frequency = <400000>;
140	pinctrl-names = "default", "gpio";
141	pinctrl-0 = <&pinctrl_i2c1_default>;
142	pinctrl-1 = <&pinctrl_i2c1_gpio>;
143	scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
144	sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
145
146	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
147	i2c-mux@74 { /* u34 */
148		compatible = "nxp,pca9548";
149		#address-cells = <1>;
150		#size-cells = <0>;
151		reg = <0x74>;
152		i2c@0 {
153			#address-cells = <1>;
154			#size-cells = <0>;
155			reg = <0>;
156			/*
157			 * IIC_EEPROM 1kB memory which uses 256B blocks
158			 * where every block has different address.
159			 *    0 - 256B address 0x54
160			 * 256B - 512B address 0x55
161			 * 512B - 768B address 0x56
162			 * 768B - 1024B address 0x57
163			 */
164			eeprom: eeprom@54 { /* u23 */
165				compatible = "atmel,24c08";
166				reg = <0x54>;
167				#address-cells = <1>;
168				#size-cells = <1>;
169			};
170		};
171
172		i2c@1 {
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <1>;
176			/* 8T49N287 - u182 */
177		};
178
179		i2c@2 {
180			#address-cells = <1>;
181			#size-cells = <0>;
182			reg = <2>;
183			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
184				compatible = "infineon,irps5401";
185				reg = <0x43>; /* pmbus / i2c 0x13 */
186			};
187			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
188				compatible = "infineon,irps5401";
189				reg = <0x44>; /* pmbus / i2c 0x14 */
190			};
191		};
192
193		i2c@4 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			reg = <4>;
197			tca6416_u97: gpio@20 {
198				compatible = "ti,tca6416";
199				reg = <0x20>;
200				gpio-controller;
201				#gpio-cells = <2>;
202				/*
203				 * IRQ not connected
204				 * Lines:
205				 * 0 - IRPS5401_ALERT_B
206				 * 1 - HDMI_8T49N241_INT_ALM
207				 * 2 - MAX6643_OT_B
208				 * 3 - MAX6643_FANFAIL_B
209				 * 5 - IIC_MUX_RESET_B
210				 * 6 - GEM3_EXP_RESET_B
211				 * 7 - FMC_LPC_PRSNT_M2C_B
212				 * 4, 10 - 17 - not connected
213				 */
214			};
215		};
216
217		i2c@5 {
218			#address-cells = <1>;
219			#size-cells = <0>;
220			reg = <5>;
221		};
222
223		i2c@7 {
224			#address-cells = <1>;
225			#size-cells = <0>;
226			reg = <7>;
227		};
228
229		/* 3, 6 not connected */
230	};
231};
232
233&pinctrl0 {
234	status = "okay";
235
236	pinctrl_can1_default: can1-default {
237		mux {
238			function = "can1";
239			groups = "can1_6_grp";
240		};
241
242		conf {
243			groups = "can1_6_grp";
244			slew-rate = <SLEW_RATE_SLOW>;
245			power-source = <IO_STANDARD_LVCMOS18>;
246			drive-strength = <12>;
247		};
248
249		conf-rx {
250			pins = "MIO25";
251			bias-high-impedance;
252		};
253
254		conf-tx {
255			pins = "MIO24";
256			bias-disable;
257		};
258	};
259
260	pinctrl_i2c1_default: i2c1-default {
261		mux {
262			groups = "i2c1_4_grp";
263			function = "i2c1";
264		};
265
266		conf {
267			groups = "i2c1_4_grp";
268			bias-pull-up;
269			slew-rate = <SLEW_RATE_SLOW>;
270			power-source = <IO_STANDARD_LVCMOS18>;
271			drive-strength = <12>;
272		};
273	};
274
275	pinctrl_i2c1_gpio: i2c1-gpio {
276		mux {
277			groups = "gpio0_16_grp", "gpio0_17_grp";
278			function = "gpio0";
279		};
280
281		conf {
282			groups = "gpio0_16_grp", "gpio0_17_grp";
283			slew-rate = <SLEW_RATE_SLOW>;
284			power-source = <IO_STANDARD_LVCMOS18>;
285			drive-strength = <12>;
286		};
287	};
288
289	pinctrl_gem3_default: gem3-default {
290		mux {
291			function = "ethernet3";
292			groups = "ethernet3_0_grp";
293		};
294
295		conf {
296			groups = "ethernet3_0_grp";
297			slew-rate = <SLEW_RATE_SLOW>;
298			power-source = <IO_STANDARD_LVCMOS18>;
299			drive-strength = <12>;
300		};
301
302		conf-rx {
303			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
304									"MIO75";
305			bias-high-impedance;
306			low-power-disable;
307		};
308
309		conf-tx {
310			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
311									"MIO69";
312			bias-disable;
313			low-power-enable;
314		};
315
316		mux-mdio {
317			function = "mdio3";
318			groups = "mdio3_0_grp";
319		};
320
321		conf-mdio {
322			groups = "mdio3_0_grp";
323			slew-rate = <SLEW_RATE_SLOW>;
324			power-source = <IO_STANDARD_LVCMOS18>;
325			bias-disable;
326		};
327	};
328
329	pinctrl_sdhci1_default: sdhci1-default {
330		mux {
331			groups = "sdio1_0_grp";
332			function = "sdio1";
333		};
334
335		conf {
336			groups = "sdio1_0_grp";
337			slew-rate = <SLEW_RATE_SLOW>;
338			power-source = <IO_STANDARD_LVCMOS18>;
339			bias-disable;
340			drive-strength = <12>;
341		};
342
343		mux-cd {
344			groups = "sdio1_cd_0_grp";
345			function = "sdio1_cd";
346		};
347
348		conf-cd {
349			groups = "sdio1_cd_0_grp";
350			bias-high-impedance;
351			bias-pull-up;
352			slew-rate = <SLEW_RATE_SLOW>;
353			power-source = <IO_STANDARD_LVCMOS18>;
354		};
355	};
356
357	pinctrl_uart0_default: uart0-default {
358		mux {
359			groups = "uart0_4_grp";
360			function = "uart0";
361		};
362
363		conf {
364			groups = "uart0_4_grp";
365			slew-rate = <SLEW_RATE_SLOW>;
366			power-source = <IO_STANDARD_LVCMOS18>;
367			drive-strength = <12>;
368		};
369
370		conf-rx {
371			pins = "MIO18";
372			bias-high-impedance;
373		};
374
375		conf-tx {
376			pins = "MIO19";
377			bias-disable;
378		};
379	};
380
381	pinctrl_uart1_default: uart1-default {
382		mux {
383			groups = "uart1_5_grp";
384			function = "uart1";
385		};
386
387		conf {
388			groups = "uart1_5_grp";
389			slew-rate = <SLEW_RATE_SLOW>;
390			power-source = <IO_STANDARD_LVCMOS18>;
391			drive-strength = <12>;
392		};
393
394		conf-rx {
395			pins = "MIO21";
396			bias-high-impedance;
397		};
398
399		conf-tx {
400			pins = "MIO20";
401			bias-disable;
402		};
403	};
404
405	pinctrl_usb0_default: usb0-default {
406		mux {
407			groups = "usb0_0_grp";
408			function = "usb0";
409		};
410
411		conf {
412			groups = "usb0_0_grp";
413			power-source = <IO_STANDARD_LVCMOS18>;
414		};
415
416		conf-rx {
417			pins = "MIO52", "MIO53", "MIO55";
418			bias-high-impedance;
419			drive-strength = <12>;
420			slew-rate = <SLEW_RATE_FAST>;
421		};
422
423		conf-tx {
424			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
425			       "MIO60", "MIO61", "MIO62", "MIO63";
426			bias-disable;
427			drive-strength = <4>;
428			slew-rate = <SLEW_RATE_SLOW>;
429		};
430	};
431};
432
433&psgtr {
434	status = "okay";
435	/* nc, sata, usb3, dp */
436	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
437	clock-names = "ref1", "ref2", "ref3";
438};
439
440&qspi {
441	status = "okay";
442	flash@0 {
443		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
444		#address-cells = <1>;
445		#size-cells = <1>;
446		reg = <0x0>;
447		spi-tx-bus-width = <4>;
448		spi-rx-bus-width = <4>;
449		spi-max-frequency = <108000000>; /* Based on DC1 spec */
450	};
451};
452
453&rtc {
454	status = "okay";
455};
456
457&sata {
458	status = "okay";
459	/* SATA OOB timing settings */
460	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
461	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
462	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
463	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
464	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
465	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
466	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
467	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
468	phy-names = "sata-phy";
469	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
470};
471
472/* SD1 with level shifter */
473&sdhci1 {
474	status = "okay";
475	no-1-8-v;
476	pinctrl-names = "default";
477	pinctrl-0 = <&pinctrl_sdhci1_default>;
478	xlnx,mio-bank = <1>;
479	disable-wp;
480};
481
482&uart0 {
483	status = "okay";
484	pinctrl-names = "default";
485	pinctrl-0 = <&pinctrl_uart0_default>;
486};
487
488&uart1 {
489	status = "okay";
490	pinctrl-names = "default";
491	pinctrl-0 = <&pinctrl_uart1_default>;
492};
493
494/* ULPI SMSC USB3320 */
495&usb0 {
496	status = "okay";
497	pinctrl-names = "default";
498	pinctrl-0 = <&pinctrl_usb0_default>;
499	phy-names = "usb3-phy";
500	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
501};
502
503&dwc3_0 {
504	status = "okay";
505	dr_mode = "host";
506	snps,usb3_lpm_capable;
507	maximum-speed = "super-speed";
508};
509
510&watchdog0 {
511	status = "okay";
512};
513
514&xilinx_ams {
515	status = "okay";
516};
517
518&ams_ps {
519	status = "okay";
520};
521
522&ams_pl {
523	status = "okay";
524};
525
526&zynqmp_dpdma {
527	status = "okay";
528};
529
530&zynqmp_dpsub {
531	status = "okay";
532	phy-names = "dp-phy0", "dp-phy1";
533	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
534	       <&psgtr 0 PHY_TYPE_DP 1 3>;
535};
536