1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3 4 * 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/phy/phy.h> 15 16/ { 17 model = "ZynqMP zc1751-xm017-dc3 RevA"; 18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 19 20 aliases { 21 ethernet0 = &gem0; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 mmc0 = &sdhci1; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 usb0 = &usb0; 29 usb1 = &usb1; 30 }; 31 32 chosen { 33 bootargs = "earlycon"; 34 stdout-path = "serial0:115200n8"; 35 }; 36 37 memory@0 { 38 device_type = "memory"; 39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 40 }; 41 42 clock_si5338_2: clk26 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <26000000>; 46 }; 47 48 clock_si5338_3: clk125 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <125000000>; 52 }; 53}; 54 55&fpd_dma_chan1 { 56 status = "okay"; 57}; 58 59&fpd_dma_chan2 { 60 status = "okay"; 61}; 62 63&fpd_dma_chan3 { 64 status = "okay"; 65}; 66 67&fpd_dma_chan4 { 68 status = "okay"; 69}; 70 71&fpd_dma_chan5 { 72 status = "okay"; 73}; 74 75&fpd_dma_chan6 { 76 status = "okay"; 77}; 78 79&fpd_dma_chan7 { 80 status = "okay"; 81}; 82 83&fpd_dma_chan8 { 84 status = "okay"; 85}; 86 87&gem0 { 88 status = "okay"; 89 phy-handle = <&phy0>; 90 phy-mode = "rgmii-id"; 91 phy0: ethernet-phy@0 { /* VSC8211 */ 92 reg = <0>; 93 }; 94}; 95 96&gpio { 97 status = "okay"; 98}; 99 100/* just eeprom here */ 101&i2c0 { 102 status = "okay"; 103 clock-frequency = <400000>; 104 105 tca6416_u26: gpio@20 { 106 compatible = "ti,tca6416"; 107 reg = <0x20>; 108 gpio-controller; 109 #gpio-cells = <2>; 110 /* IRQ not connected */ 111 }; 112 113 rtc@68 { 114 compatible = "dallas,ds1339"; 115 reg = <0x68>; 116 }; 117}; 118 119/* eeprom24c02 and SE98A temp chip pca9306 */ 120&i2c1 { 121 status = "okay"; 122 clock-frequency = <400000>; 123}; 124 125/* MT29F64G08AECDBJ4-6 */ 126&nand0 { 127 status = "okay"; 128 arasan,has-mdma; 129 num-cs = <2>; 130}; 131 132&psgtr { 133 status = "okay"; 134 /* usb3, sata */ 135 clocks = <&clock_si5338_2>, <&clock_si5338_3>; 136 clock-names = "ref2", "ref3"; 137}; 138 139&rtc { 140 status = "okay"; 141}; 142 143&sata { 144 status = "okay"; 145 /* SATA phy OOB timing settings */ 146 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; 147 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; 148 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 149 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 150 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; 151 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; 152 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 153 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 154 phy-names = "sata-phy"; 155 phys = <&psgtr 2 PHY_TYPE_SATA 0 3>; 156}; 157 158&sdhci1 { /* emmc with some settings */ 159 status = "okay"; 160}; 161 162/* main */ 163&uart0 { 164 status = "okay"; 165}; 166 167/* DB9 */ 168&uart1 { 169 status = "okay"; 170}; 171 172&usb0 { 173 status = "okay"; 174 phy-names = "usb3-phy"; 175 phys = <&psgtr 0 PHY_TYPE_USB3 0 2>; 176}; 177 178&dwc3_0 { 179 status = "okay"; 180 dr_mode = "host"; 181 snps,usb3_lpm_capable; 182 maximum-speed = "super-speed"; 183}; 184 185/* ULPI SMSC USB3320 */ 186&usb1 { 187 status = "okay"; 188 phy-names = "usb3-phy"; 189 phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; 190}; 191 192&dwc3_1 { 193 status = "okay"; 194 dr_mode = "host"; 195 snps,usb3_lpm_capable; 196 maximum-speed = "super-speed"; 197}; 198