1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 4 * 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-clk-ccf.dtsi" 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17 18/ { 19 model = "ZynqMP zc1751-xm016-dc2 RevA"; 20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem2; 24 i2c0 = &i2c0; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 usb0 = &usb1; 31 }; 32 33 chosen { 34 bootargs = "earlycon"; 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 memory@0 { 39 device_type = "memory"; 40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 41 }; 42}; 43 44&can0 { 45 status = "okay"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_can0_default>; 48}; 49 50&can1 { 51 status = "okay"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_can1_default>; 54}; 55 56&fpd_dma_chan1 { 57 status = "okay"; 58}; 59 60&fpd_dma_chan2 { 61 status = "okay"; 62}; 63 64&fpd_dma_chan3 { 65 status = "okay"; 66}; 67 68&fpd_dma_chan4 { 69 status = "okay"; 70}; 71 72&fpd_dma_chan5 { 73 status = "okay"; 74}; 75 76&fpd_dma_chan6 { 77 status = "okay"; 78}; 79 80&fpd_dma_chan7 { 81 status = "okay"; 82}; 83 84&fpd_dma_chan8 { 85 status = "okay"; 86}; 87 88&gem2 { 89 status = "okay"; 90 phy-handle = <&phy0>; 91 phy-mode = "rgmii-id"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_gem2_default>; 94 phy0: ethernet-phy@5 { 95 reg = <5>; 96 ti,rx-internal-delay = <0x8>; 97 ti,tx-internal-delay = <0xa>; 98 ti,fifo-depth = <0x1>; 99 ti,dp83867-rxctrl-strap-quirk; 100 }; 101}; 102 103&gpio { 104 status = "okay"; 105}; 106 107&i2c0 { 108 status = "okay"; 109 clock-frequency = <400000>; 110 pinctrl-names = "default", "gpio"; 111 pinctrl-0 = <&pinctrl_i2c0_default>; 112 pinctrl-1 = <&pinctrl_i2c0_gpio>; 113 scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; 114 sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; 115 116 tca6416_u26: gpio@20 { 117 compatible = "ti,tca6416"; 118 reg = <0x20>; 119 gpio-controller; 120 #gpio-cells = <2>; 121 /* IRQ not connected */ 122 }; 123 124 rtc@68 { 125 compatible = "dallas,ds1339"; 126 reg = <0x68>; 127 }; 128}; 129 130&nand0 { 131 status = "okay"; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_nand0_default>; 134 arasan,has-mdma; 135 136 nand@0 { 137 reg = <0x0>; 138 #address-cells = <0x2>; 139 #size-cells = <0x1>; 140 nand-ecc-mode = "soft"; 141 nand-ecc-algo = "bch"; 142 nand-rb = <0>; 143 label = "main-storage-0"; 144 }; 145 nand@1 { 146 reg = <0x1>; 147 #address-cells = <0x2>; 148 #size-cells = <0x1>; 149 nand-ecc-mode = "soft"; 150 nand-ecc-algo = "bch"; 151 nand-rb = <0>; 152 label = "main-storage-1"; 153 }; 154}; 155 156&pinctrl0 { 157 status = "okay"; 158 pinctrl_can0_default: can0-default { 159 mux { 160 function = "can0"; 161 groups = "can0_9_grp"; 162 }; 163 164 conf { 165 groups = "can0_9_grp"; 166 slew-rate = <SLEW_RATE_SLOW>; 167 power-source = <IO_STANDARD_LVCMOS18>; 168 }; 169 170 conf-rx { 171 pins = "MIO38"; 172 bias-high-impedance; 173 }; 174 175 conf-tx { 176 pins = "MIO39"; 177 bias-disable; 178 }; 179 }; 180 181 pinctrl_can1_default: can1-default { 182 mux { 183 function = "can1"; 184 groups = "can1_8_grp"; 185 }; 186 187 conf { 188 groups = "can1_8_grp"; 189 slew-rate = <SLEW_RATE_SLOW>; 190 power-source = <IO_STANDARD_LVCMOS18>; 191 }; 192 193 conf-rx { 194 pins = "MIO33"; 195 bias-high-impedance; 196 }; 197 198 conf-tx { 199 pins = "MIO32"; 200 bias-disable; 201 }; 202 }; 203 204 pinctrl_i2c0_default: i2c0-default { 205 mux { 206 groups = "i2c0_1_grp"; 207 function = "i2c0"; 208 }; 209 210 conf { 211 groups = "i2c0_1_grp"; 212 bias-pull-up; 213 slew-rate = <SLEW_RATE_SLOW>; 214 power-source = <IO_STANDARD_LVCMOS18>; 215 }; 216 }; 217 218 pinctrl_i2c0_gpio: i2c0-gpio { 219 mux { 220 groups = "gpio0_6_grp", "gpio0_7_grp"; 221 function = "gpio0"; 222 }; 223 224 conf { 225 groups = "gpio0_6_grp", "gpio0_7_grp"; 226 slew-rate = <SLEW_RATE_SLOW>; 227 power-source = <IO_STANDARD_LVCMOS18>; 228 }; 229 }; 230 231 pinctrl_uart0_default: uart0-default { 232 mux { 233 groups = "uart0_10_grp"; 234 function = "uart0"; 235 }; 236 237 conf { 238 groups = "uart0_10_grp"; 239 slew-rate = <SLEW_RATE_SLOW>; 240 power-source = <IO_STANDARD_LVCMOS18>; 241 }; 242 243 conf-rx { 244 pins = "MIO42"; 245 bias-high-impedance; 246 }; 247 248 conf-tx { 249 pins = "MIO43"; 250 bias-disable; 251 }; 252 }; 253 254 pinctrl_uart1_default: uart1-default { 255 mux { 256 groups = "uart1_10_grp"; 257 function = "uart1"; 258 }; 259 260 conf { 261 groups = "uart1_10_grp"; 262 slew-rate = <SLEW_RATE_SLOW>; 263 power-source = <IO_STANDARD_LVCMOS18>; 264 }; 265 266 conf-rx { 267 pins = "MIO41"; 268 bias-high-impedance; 269 }; 270 271 conf-tx { 272 pins = "MIO40"; 273 bias-disable; 274 }; 275 }; 276 277 pinctrl_usb1_default: usb1-default { 278 mux { 279 groups = "usb1_0_grp"; 280 function = "usb1"; 281 }; 282 283 conf { 284 groups = "usb1_0_grp"; 285 power-source = <IO_STANDARD_LVCMOS18>; 286 }; 287 288 conf-rx { 289 pins = "MIO64", "MIO65", "MIO67"; 290 bias-high-impedance; 291 drive-strength = <12>; 292 slew-rate = <SLEW_RATE_FAST>; 293 }; 294 295 conf-tx { 296 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", 297 "MIO72", "MIO73", "MIO74", "MIO75"; 298 bias-disable; 299 drive-strength = <4>; 300 slew-rate = <SLEW_RATE_SLOW>; 301 }; 302 }; 303 304 pinctrl_gem2_default: gem2-default { 305 mux { 306 function = "ethernet2"; 307 groups = "ethernet2_0_grp"; 308 }; 309 310 conf { 311 groups = "ethernet2_0_grp"; 312 slew-rate = <SLEW_RATE_SLOW>; 313 power-source = <IO_STANDARD_LVCMOS18>; 314 }; 315 316 conf-rx { 317 pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", 318 "MIO63"; 319 bias-high-impedance; 320 low-power-disable; 321 }; 322 323 conf-tx { 324 pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", 325 "MIO57"; 326 bias-disable; 327 low-power-enable; 328 }; 329 330 mux-mdio { 331 function = "mdio2"; 332 groups = "mdio2_0_grp"; 333 }; 334 335 conf-mdio { 336 groups = "mdio2_0_grp"; 337 slew-rate = <SLEW_RATE_SLOW>; 338 power-source = <IO_STANDARD_LVCMOS18>; 339 bias-disable; 340 }; 341 }; 342 343 pinctrl_nand0_default: nand0-default { 344 mux { 345 groups = "nand0_0_grp"; 346 function = "nand0"; 347 }; 348 349 conf { 350 groups = "nand0_0_grp"; 351 bias-pull-up; 352 }; 353 354 mux-ce { 355 groups = "nand0_ce_0_grp"; 356 function = "nand0_ce"; 357 }; 358 359 conf-ce { 360 groups = "nand0_ce_0_grp"; 361 bias-pull-up; 362 }; 363 364 mux-rb { 365 groups = "nand0_rb_0_grp"; 366 function = "nand0_rb"; 367 }; 368 369 conf-rb { 370 groups = "nand0_rb_0_grp"; 371 bias-pull-up; 372 }; 373 374 mux-dqs { 375 groups = "nand0_dqs_0_grp"; 376 function = "nand0_dqs"; 377 }; 378 379 conf-dqs { 380 groups = "nand0_dqs_0_grp"; 381 bias-pull-up; 382 }; 383 }; 384 385 pinctrl_spi0_default: spi0-default { 386 mux { 387 groups = "spi0_0_grp"; 388 function = "spi0"; 389 }; 390 391 conf { 392 groups = "spi0_0_grp"; 393 bias-disable; 394 slew-rate = <SLEW_RATE_SLOW>; 395 power-source = <IO_STANDARD_LVCMOS18>; 396 }; 397 398 mux-cs { 399 groups = "spi0_ss_0_grp", "spi0_ss_1_grp", 400 "spi0_ss_2_grp"; 401 function = "spi0_ss"; 402 }; 403 404 conf-cs { 405 groups = "spi0_ss_0_grp", "spi0_ss_1_grp", 406 "spi0_ss_2_grp"; 407 bias-disable; 408 }; 409 }; 410 411 pinctrl_spi1_default: spi1-default { 412 mux { 413 groups = "spi1_3_grp"; 414 function = "spi1"; 415 }; 416 417 conf { 418 groups = "spi1_3_grp"; 419 bias-disable; 420 slew-rate = <SLEW_RATE_SLOW>; 421 power-source = <IO_STANDARD_LVCMOS18>; 422 }; 423 424 mux-cs { 425 groups = "spi1_ss_9_grp", "spi1_ss_10_grp", 426 "spi1_ss_11_grp"; 427 function = "spi1_ss"; 428 }; 429 430 conf-cs { 431 groups = "spi1_ss_9_grp", "spi1_ss_10_grp", 432 "spi1_ss_11_grp"; 433 bias-disable; 434 }; 435 }; 436}; 437 438&rtc { 439 status = "okay"; 440}; 441 442&spi0 { 443 status = "okay"; 444 num-cs = <1>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_spi0_default>; 447 448 spi0_flash0: flash@0 { 449 #address-cells = <1>; 450 #size-cells = <1>; 451 compatible = "sst,sst25wf080", "jedec,spi-nor"; 452 spi-max-frequency = <50000000>; 453 reg = <0>; 454 455 partition@0 { 456 label = "spi0-data"; 457 reg = <0x0 0x100000>; 458 }; 459 }; 460}; 461 462&spi1 { 463 status = "okay"; 464 num-cs = <1>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pinctrl_spi1_default>; 467 468 spi1_flash0: flash@0 { 469 #address-cells = <1>; 470 #size-cells = <1>; 471 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; 472 spi-max-frequency = <20000000>; 473 reg = <0>; 474 475 partition@0 { 476 label = "spi1-data"; 477 reg = <0x0 0x84000>; 478 }; 479 }; 480}; 481 482/* ULPI SMSC USB3320 */ 483&usb1 { 484 status = "okay"; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_usb1_default>; 487}; 488 489&dwc3_1 { 490 status = "okay"; 491 dr_mode = "host"; 492}; 493 494&uart0 { 495 status = "okay"; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&pinctrl_uart0_default>; 498}; 499 500&uart1 { 501 status = "okay"; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_uart1_default>; 504}; 505