1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZC1232 4 * 5 * (C) Copyright 2017 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14 15/ { 16 model = "ZynqMP ZC1232 RevA"; 17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; 18 19 aliases { 20 serial0 = &uart0; 21 serial1 = &dcc; 22 }; 23 24 chosen { 25 bootargs = "earlycon"; 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@0 { 30 device_type = "memory"; 31 reg = <0x0 0x0 0x0 0x80000000>; 32 }; 33}; 34 35&dcc { 36 status = "okay"; 37}; 38 39&sata { 40 status = "okay"; 41 /* SATA OOB timing settings */ 42 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 43 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 44 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 45 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 46 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 47 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 48 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 49 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 50}; 51 52&uart0 { 53 status = "okay"; 54}; 55