1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A 4 * 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/phy/phy.h> 17 18/ { 19 model = "ZynqMP SM-K26 Rev1/B/A"; 20 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", 21 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", 22 "xlnx,zynqmp"; 23 24 aliases { 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci0; 28 mmc1 = &sdhci1; 29 nvmem0 = &eeprom; 30 nvmem1 = &eeprom_cc; 31 rtc0 = &rtc; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &dcc; 35 spi0 = &qspi; 36 spi1 = &spi0; 37 spi2 = &spi1; 38 usb0 = &usb0; 39 usb1 = &usb1; 40 }; 41 42 chosen { 43 bootargs = "earlycon"; 44 stdout-path = "serial1:115200n8"; 45 }; 46 47 memory@0 { 48 device_type = "memory"; /* 4GB */ 49 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 50 }; 51 52 gpio-keys { 53 compatible = "gpio-keys"; 54 autorepeat; 55 key-fwuen { 56 label = "fwuen"; 57 gpios = <&gpio 12 GPIO_ACTIVE_LOW>; 58 }; 59 }; 60 61 leds { 62 compatible = "gpio-leds"; 63 ds35-led { 64 label = "heartbeat"; 65 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; 66 linux,default-trigger = "heartbeat"; 67 }; 68 69 ds36-led { 70 label = "vbus_det"; 71 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; 72 default-state = "on"; 73 }; 74 }; 75}; 76 77&uart1 { /* MIO36/MIO37 */ 78 status = "okay"; 79}; 80 81&qspi { /* MIO 0-5 - U143 */ 82 status = "okay"; 83 flash@0 { /* MT25QU512A */ 84 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ 85 #address-cells = <1>; 86 #size-cells = <1>; 87 reg = <0>; 88 spi-tx-bus-width = <1>; 89 spi-rx-bus-width = <4>; 90 spi-max-frequency = <40000000>; /* 40MHz */ 91 partition@0 { 92 label = "Image Selector"; 93 reg = <0x0 0x80000>; /* 512KB */ 94 read-only; 95 lock; 96 }; 97 partition@80000 { 98 label = "Image Selector Golden"; 99 reg = <0x80000 0x80000>; /* 512KB */ 100 read-only; 101 lock; 102 }; 103 partition@100000 { 104 label = "Persistent Register"; 105 reg = <0x100000 0x20000>; /* 128KB */ 106 }; 107 partition@120000 { 108 label = "Persistent Register Backup"; 109 reg = <0x120000 0x20000>; /* 128KB */ 110 }; 111 partition@140000 { 112 label = "Open_1"; 113 reg = <0x140000 0xC0000>; /* 768KB */ 114 }; 115 partition@200000 { 116 label = "Image A (FSBL, PMU, ATF, U-Boot)"; 117 reg = <0x200000 0xD00000>; /* 13MB */ 118 }; 119 partition@f00000 { 120 label = "ImgSel Image A Catch"; 121 reg = <0xF00000 0x80000>; /* 512KB */ 122 read-only; 123 lock; 124 }; 125 partition@f80000 { 126 label = "Image B (FSBL, PMU, ATF, U-Boot)"; 127 reg = <0xF80000 0xD00000>; /* 13MB */ 128 }; 129 partition@1c80000 { 130 label = "ImgSel Image B Catch"; 131 reg = <0x1C80000 0x80000>; /* 512KB */ 132 read-only; 133 lock; 134 }; 135 partition@1d00000 { 136 label = "Open_2"; 137 reg = <0x1D00000 0x100000>; /* 1MB */ 138 }; 139 partition@1e00000 { 140 label = "Recovery Image"; 141 reg = <0x1E00000 0x200000>; /* 2MB */ 142 read-only; 143 lock; 144 }; 145 partition@2000000 { 146 label = "Recovery Image Backup"; 147 reg = <0x2000000 0x200000>; /* 2MB */ 148 read-only; 149 lock; 150 }; 151 partition@2200000 { 152 label = "U-Boot storage variables"; 153 reg = <0x2200000 0x20000>; /* 128KB */ 154 }; 155 partition@2220000 { 156 label = "U-Boot storage variables backup"; 157 reg = <0x2220000 0x20000>; /* 128KB */ 158 }; 159 partition@2240000 { 160 label = "SHA256"; 161 reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ 162 read-only; 163 lock; 164 }; 165 partition@2250000 { 166 label = "User"; 167 reg = <0x2250000 0x1db0000>; /* 29.5 MB */ 168 }; 169 }; 170}; 171 172&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ 173 status = "okay"; 174 non-removable; 175 disable-wp; 176 bus-width = <8>; 177 xlnx,mio-bank = <0>; 178}; 179 180&spi1 { /* MIO6, 9-11 */ 181 status = "okay"; 182 label = "TPM"; 183 num-cs = <1>; 184 tpm@0 { /* slm9670 - U144 */ 185 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 186 reg = <0>; 187 spi-max-frequency = <18500000>; 188 }; 189}; 190 191&i2c1 { 192 status = "okay"; 193 clock-frequency = <400000>; 194 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 195 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 196 197 eeprom: eeprom@50 { /* u46 - also at address 0x58 */ 198 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ 199 reg = <0x50>; 200 /* WP pin EE_WP_EN connected to slg7x644092@68 */ 201 }; 202 203 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ 204 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ 205 reg = <0x51>; 206 }; 207 208 /* da9062@30 - u170 - also at address 0x31 */ 209 /* da9131@33 - u167 */ 210 da9131: pmic@33 { 211 compatible = "dlg,da9131"; 212 reg = <0x33>; 213 regulators { 214 da9131_buck1: buck1 { 215 regulator-name = "da9131_buck1"; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 da9131_buck2: buck2 { 220 regulator-name = "da9131_buck2"; 221 regulator-boot-on; 222 regulator-always-on; 223 }; 224 }; 225 }; 226 227 /* da9130@32 - u166 */ 228 da9130: pmic@32 { 229 compatible = "dlg,da9130"; 230 reg = <0x32>; 231 regulators { 232 da9130_buck1: buck1 { 233 regulator-name = "da9130_buck1"; 234 regulator-boot-on; 235 regulator-always-on; 236 }; 237 }; 238 }; 239 240 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ 241 /* 242 * stdp4320 - u27 FW has below two issues to be fixed in next board revision. 243 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. 244 * Address conflict with slg7x644091@70 making both the devices NOT accessible. 245 * With the FW fix, stdp4320 should respond to address 0x73 only. 246 */ 247 /* slg7x644092@68 - u169 */ 248 /* Also connected via JA1C as C23/C24 */ 249}; 250 251&gpio { 252 status = "okay"; 253 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ 254 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ 255 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ 256 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ 257 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ 258 "I2C1_SDA", "", "", "", "", /* 25 - 29 */ 259 "", "", "", "", "", /* 30 - 34 */ 260 "", "", "", "", "", /* 35 - 39 */ 261 "", "", "", "", "", /* 40 - 44 */ 262 "", "", "", "", "", /* 45 - 49 */ 263 "", "", "", "", "", /* 50 - 54 */ 264 "", "", "", "", "", /* 55 - 59 */ 265 "", "", "", "", "", /* 60 - 64 */ 266 "", "", "", "", "", /* 65 - 69 */ 267 "", "", "", "", "", /* 70 - 74 */ 268 "", "", "", /* 75 - 77, MIO end and EMIO start */ 269 "", "", /* 78 - 79 */ 270 "", "", "", "", "", /* 80 - 84 */ 271 "", "", "", "", "", /* 85 - 89 */ 272 "", "", "", "", "", /* 90 - 94 */ 273 "", "", "", "", "", /* 95 - 99 */ 274 "", "", "", "", "", /* 100 - 104 */ 275 "", "", "", "", "", /* 105 - 109 */ 276 "", "", "", "", "", /* 110 - 114 */ 277 "", "", "", "", "", /* 115 - 119 */ 278 "", "", "", "", "", /* 120 - 124 */ 279 "", "", "", "", "", /* 125 - 129 */ 280 "", "", "", "", "", /* 130 - 134 */ 281 "", "", "", "", "", /* 135 - 139 */ 282 "", "", "", "", "", /* 140 - 144 */ 283 "", "", "", "", "", /* 145 - 149 */ 284 "", "", "", "", "", /* 150 - 154 */ 285 "", "", "", "", "", /* 155 - 159 */ 286 "", "", "", "", "", /* 160 - 164 */ 287 "", "", "", "", "", /* 165 - 169 */ 288 "", "", "", ""; /* 170 - 173 */ 289}; 290