xref: /freebsd/sys/contrib/device-tree/src/arm64/xilinx/zynqmp-sm-k26-revA.dts (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18
19/ {
20	model = "ZynqMP SM-K26 Rev1/B/A";
21	compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
22		     "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
23		     "xlnx,zynqmp";
24
25	aliases {
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		mmc0 = &sdhci0;
29		mmc1 = &sdhci1;
30		nvmem0 = &eeprom;
31		nvmem1 = &eeprom_cc;
32		rtc0 = &rtc;
33		serial0 = &uart0;
34		serial1 = &uart1;
35		serial2 = &dcc;
36		spi0 = &qspi;
37		spi1 = &spi0;
38		spi2 = &spi1;
39		usb0 = &usb0;
40		usb1 = &usb1;
41	};
42
43	chosen {
44		bootargs = "earlycon";
45		stdout-path = "serial1:115200n8";
46	};
47
48	memory@0 {
49		device_type = "memory"; /* 4GB */
50		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
51	};
52
53	gpio-keys {
54		compatible = "gpio-keys";
55		autorepeat;
56		key-fwuen {
57			label = "fwuen";
58			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
59			linux,code = <BTN_MISC>;
60			wakeup-source;
61			autorepeat;
62		};
63	};
64
65	leds {
66		compatible = "gpio-leds";
67		ds35-led {
68			label = "heartbeat";
69			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
70			linux,default-trigger = "heartbeat";
71		};
72
73		ds36-led {
74			label = "vbus_det";
75			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
76			default-state = "on";
77		};
78	};
79
80	ams {
81		compatible = "iio-hwmon";
82		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
83			<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
84			<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
85			<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
86			<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
87			<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
88			<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
89			<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
90			<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
91			<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
92	};
93};
94
95&modepin_gpio {
96	label = "modepin";
97};
98
99&uart1 { /* MIO36/MIO37 */
100	status = "okay";
101};
102
103&pinctrl0 {
104	status = "okay";
105	pinctrl_sdhci0_default: sdhci0-default {
106		conf {
107			groups = "sdio0_0_grp";
108			slew-rate = <SLEW_RATE_SLOW>;
109			power-source = <IO_STANDARD_LVCMOS18>;
110			bias-disable;
111		};
112
113		mux {
114			groups = "sdio0_0_grp";
115			function = "sdio0";
116		};
117	};
118};
119
120&qspi { /* MIO 0-5 - U143 */
121	status = "okay";
122	spi_flash: flash@0 { /* MT25QU512A */
123		compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
124		#address-cells = <1>;
125		#size-cells = <1>;
126		reg = <0>;
127		spi-tx-bus-width = <4>;
128		spi-rx-bus-width = <4>;
129		spi-max-frequency = <40000000>; /* 40MHz */
130
131		partitions {
132			compatible = "fixed-partitions";
133			#address-cells = <1>;
134			#size-cells = <1>;
135
136			partition@0 {
137				label = "Image Selector";
138				reg = <0x0 0x80000>; /* 512KB */
139				read-only;
140				lock;
141			};
142			partition@80000 {
143				label = "Image Selector Golden";
144				reg = <0x80000 0x80000>; /* 512KB */
145				read-only;
146				lock;
147			};
148			partition@100000 {
149				label = "Persistent Register";
150				reg = <0x100000 0x20000>; /* 128KB */
151			};
152			partition@120000 {
153				label = "Persistent Register Backup";
154				reg = <0x120000 0x20000>; /* 128KB */
155			};
156			partition@140000 {
157				label = "Open_1";
158				reg = <0x140000 0xC0000>; /* 768KB */
159			};
160			partition@200000 {
161				label = "Image A (FSBL, PMU, ATF, U-Boot)";
162				reg = <0x200000 0xD00000>; /* 13MB */
163			};
164			partition@f00000 {
165				label = "ImgSel Image A Catch";
166				reg = <0xF00000 0x80000>; /* 512KB */
167				read-only;
168				lock;
169			};
170			partition@f80000 {
171				label = "Image B (FSBL, PMU, ATF, U-Boot)";
172				reg = <0xF80000 0xD00000>; /* 13MB */
173			};
174			partition@1c80000 {
175				label = "ImgSel Image B Catch";
176				reg = <0x1C80000 0x80000>; /* 512KB */
177				read-only;
178				lock;
179			};
180			partition@1d00000 {
181				label = "Open_2";
182				reg = <0x1D00000 0x100000>; /* 1MB */
183			};
184			partition@1e00000 {
185				label = "Recovery Image";
186				reg = <0x1E00000 0x200000>; /* 2MB */
187				read-only;
188				lock;
189			};
190			partition@2000000 {
191				label = "Recovery Image Backup";
192				reg = <0x2000000 0x200000>; /* 2MB */
193				read-only;
194				lock;
195			};
196			partition@2200000 {
197				label = "U-Boot storage variables";
198				reg = <0x2200000 0x20000>; /* 128KB */
199			};
200			partition@2220000 {
201				label = "U-Boot storage variables backup";
202				reg = <0x2220000 0x20000>; /* 128KB */
203			};
204			partition@2240000 {
205				label = "SHA256";
206				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
207				read-only;
208				lock;
209			};
210			partition@2280000 {
211				label = "Secure OS Storage";
212				reg = <0x2280000 0x20000>; /* 128KB */
213			};
214			partition@22A0000 {
215				label = "User";
216				reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
217			};
218		};
219	};
220};
221
222&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
223	status = "okay";
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_sdhci0_default>;
226	non-removable;
227	disable-wp;
228	bus-width = <8>;
229	xlnx,mio-bank = <0>;
230	assigned-clock-rates = <187498123>;
231};
232
233&spi1 { /* MIO6, 9-11 */
234	status = "okay";
235	label = "TPM";
236	num-cs = <1>;
237	tpm@0 { /* slm9670 - U144 */
238		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
239		reg = <0>;
240		spi-max-frequency = <18500000>;
241	};
242};
243
244&i2c1 {
245	status = "okay";
246	bootph-all;
247	clock-frequency = <400000>;
248	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
249	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
250
251	eeprom: eeprom@50 { /* u46 - also at address 0x58 */
252		bootph-all;
253		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
254		reg = <0x50>;
255		/* WP pin EE_WP_EN connected to slg7x644092@68 */
256	};
257
258	eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
259		bootph-all;
260		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
261		reg = <0x51>;
262	};
263
264	/* da9062@30 - u170 - also at address 0x31 */
265	/* da9131@33 - u167 */
266	da9131: pmic@33 {
267		compatible = "dlg,da9131";
268		reg = <0x33>;
269		regulators {
270			da9131_buck1: buck1 {
271				regulator-name = "da9131_buck1";
272				regulator-boot-on;
273				regulator-always-on;
274			};
275			da9131_buck2: buck2 {
276				regulator-name = "da9131_buck2";
277				regulator-boot-on;
278				regulator-always-on;
279			};
280		};
281	};
282
283	/* da9130@32 - u166 */
284	da9130: pmic@32 {
285		compatible = "dlg,da9130";
286		reg = <0x32>;
287		regulators {
288			da9130_buck1: buck1 {
289				regulator-name = "da9130_buck1";
290				regulator-boot-on;
291				regulator-always-on;
292			};
293		};
294	};
295
296	/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
297	/*
298	 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
299	 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
300	 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
301	 * With the FW fix, stdp4320 should respond to address 0x73 only.
302	 */
303	/* slg7x644092@68 - u169 */
304	/* Also connected via JA1C as C23/C24 */
305};
306
307&gpio {
308	status = "okay";
309	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
310			  "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
311			  "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
312			  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
313			  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
314			  "I2C1_SDA", "", "", "", "", /* 25 - 29 */
315			  "", "", "", "", "", /* 30 - 34 */
316			  "", "", "", "", "", /* 35 - 39 */
317			  "", "", "", "", "", /* 40 - 44 */
318			  "", "", "", "", "", /* 45 - 49 */
319			  "", "", "", "", "", /* 50 - 54 */
320			  "", "", "", "", "", /* 55 - 59 */
321			  "", "", "", "", "", /* 60 - 64 */
322			  "", "", "", "", "", /* 65 - 69 */
323			  "", "", "", "", "", /* 70 - 74 */
324			  "", "", "", /* 75 - 77, MIO end and EMIO start */
325			  "", "", /* 78 - 79 */
326			  "", "", "", "", "", /* 80 - 84 */
327			  "", "", "", "", "", /* 85 - 89 */
328			  "", "", "", "", "", /* 90 - 94 */
329			  "", "", "", "", "", /* 95 - 99 */
330			  "", "", "", "", "", /* 100 - 104 */
331			  "", "", "", "", "", /* 105 - 109 */
332			  "", "", "", "", "", /* 110 - 114 */
333			  "", "", "", "", "", /* 115 - 119 */
334			  "", "", "", "", "", /* 120 - 124 */
335			  "", "", "", "", "", /* 125 - 129 */
336			  "", "", "", "", "", /* 130 - 134 */
337			  "", "", "", "", "", /* 135 - 139 */
338			  "", "", "", "", "", /* 140 - 144 */
339			  "", "", "", "", "", /* 145 - 149 */
340			  "", "", "", "", "", /* 150 - 154 */
341			  "", "", "", "", "", /* 155 - 159 */
342			  "", "", "", "", "", /* 160 - 164 */
343			  "", "", "", "", "", /* 165 - 169 */
344			  "", "", "", ""; /* 170 - 173 */
345};
346
347&xilinx_ams {
348	status = "okay";
349};
350
351&ams_ps {
352	status = "okay";
353};
354
355&ams_pl {
356	status = "okay";
357};
358
359&zynqmp_dpsub {
360	status = "okay";
361};
362
363&rtc {
364	status = "okay";
365};
366
367&lpd_dma_chan1 {
368	status = "okay";
369};
370
371&lpd_dma_chan2 {
372	status = "okay";
373};
374
375&lpd_dma_chan3 {
376	status = "okay";
377};
378
379&lpd_dma_chan4 {
380	status = "okay";
381};
382
383&lpd_dma_chan5 {
384	status = "okay";
385};
386
387&lpd_dma_chan6 {
388	status = "okay";
389};
390
391&lpd_dma_chan7 {
392	status = "okay";
393};
394
395&lpd_dma_chan8 {
396	status = "okay";
397};
398
399&fpd_dma_chan1 {
400	status = "okay";
401};
402
403&fpd_dma_chan2 {
404	status = "okay";
405};
406
407&fpd_dma_chan3 {
408	status = "okay";
409};
410
411&fpd_dma_chan4 {
412	status = "okay";
413};
414
415&fpd_dma_chan5 {
416	status = "okay";
417};
418
419&fpd_dma_chan6 {
420	status = "okay";
421};
422
423&fpd_dma_chan7 {
424	status = "okay";
425};
426
427&fpd_dma_chan8 {
428	status = "okay";
429};
430
431&gpu {
432	status = "okay";
433};
434
435&lpd_watchdog {
436	status = "okay";
437};
438
439&watchdog0 {
440	status = "okay";
441};
442
443&cpu_opp_table {
444	opp00 {
445		opp-hz = /bits/ 64 <1333333333>;
446	};
447	opp01 {
448		opp-hz = /bits/ 64 <666666666>;
449	};
450	opp02 {
451		opp-hz = /bits/ 64 <444444444>;
452	};
453	opp03 {
454		opp-hz = /bits/ 64 <333333333>;
455	};
456};
457