1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 15/dts-v1/; 16/plugin/; 17 18&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 19 #address-cells = <1>; 20 #size-cells = <0>; 21 pinctrl-names = "default", "gpio"; 22 pinctrl-0 = <&pinctrl_i2c1_default>; 23 pinctrl-1 = <&pinctrl_i2c1_gpio>; 24 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 25 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 26 27 /* u14 - 0x40 - ina260 */ 28 /* u43 - 0x2d - usb5744 */ 29 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 30}; 31 32&amba { 33 si5332_0: si5332_0 { /* u17 */ 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <125000000>; 37 }; 38 39 si5332_1: si5332_1 { /* u17 */ 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <25000000>; 43 }; 44 45 si5332_2: si5332_2 { /* u17 */ 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <48000000>; 49 }; 50 51 si5332_3: si5332_3 { /* u17 */ 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <24000000>; 55 }; 56 57 si5332_4: si5332_4 { /* u17 */ 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <26000000>; 61 }; 62 63 si5332_5: si5332_5 { /* u17 */ 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <27000000>; 67 }; 68}; 69 70/* DP/USB 3.0 */ 71&psgtr { 72 status = "okay"; 73 /* pcie, usb3, sata */ 74 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 75 clock-names = "ref0", "ref1", "ref2"; 76}; 77 78&zynqmp_dpsub { 79 status = "disabled"; 80 phy-names = "dp-phy0", "dp-phy1"; 81 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 82}; 83 84&zynqmp_dpdma { 85 status = "okay"; 86}; 87 88&usb0 { 89 status = "okay"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_usb0_default>; 92 phy-names = "usb3-phy"; 93 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 94}; 95 96&dwc3_0 { 97 status = "okay"; 98 dr_mode = "host"; 99 snps,usb3_lpm_capable; 100 maximum-speed = "super-speed"; 101}; 102 103&sdhci1 { /* on CC with tuned parameters */ 104 status = "okay"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_sdhci1_default>; 107 /* 108 * SD 3.0 requires level shifter and this property 109 * should be removed if the board has level shifter and 110 * need to work in UHS mode 111 */ 112 no-1-8-v; 113 disable-wp; 114 xlnx,mio-bank = <1>; 115 clk-phase-sd-hs = <126>, <60>; 116 clk-phase-uhs-sdr25 = <120>, <60>; 117 clk-phase-uhs-ddr50 = <126>, <48>; 118}; 119 120&gem3 { /* required by spec */ 121 status = "okay"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_gem3_default>; 124 phy-handle = <&phy0>; 125 phy-mode = "rgmii-id"; 126 127 mdio: mdio { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 131 reset-delay-us = <2>; 132 133 phy0: ethernet-phy@1 { 134 #phy-cells = <1>; 135 reg = <1>; 136 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 137 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 138 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 139 ti,dp83867-rxctrl-strap-quirk; 140 }; 141 }; 142}; 143 144&pinctrl0 { /* required by spec */ 145 status = "okay"; 146 147 pinctrl_uart1_default: uart1-default { 148 conf { 149 groups = "uart1_9_grp"; 150 slew-rate = <SLEW_RATE_SLOW>; 151 power-source = <IO_STANDARD_LVCMOS18>; 152 drive-strength = <12>; 153 }; 154 155 conf-rx { 156 pins = "MIO37"; 157 bias-high-impedance; 158 }; 159 160 conf-tx { 161 pins = "MIO36"; 162 bias-disable; 163 }; 164 165 mux { 166 groups = "uart1_9_grp"; 167 function = "uart1"; 168 }; 169 }; 170 171 pinctrl_i2c1_default: i2c1-default { 172 conf { 173 groups = "i2c1_6_grp"; 174 bias-pull-up; 175 slew-rate = <SLEW_RATE_SLOW>; 176 power-source = <IO_STANDARD_LVCMOS18>; 177 }; 178 179 mux { 180 groups = "i2c1_6_grp"; 181 function = "i2c1"; 182 }; 183 }; 184 185 pinctrl_i2c1_gpio: i2c1-gpio { 186 conf { 187 groups = "gpio0_24_grp", "gpio0_25_grp"; 188 slew-rate = <SLEW_RATE_SLOW>; 189 power-source = <IO_STANDARD_LVCMOS18>; 190 }; 191 192 mux { 193 groups = "gpio0_24_grp", "gpio0_25_grp"; 194 function = "gpio0"; 195 }; 196 }; 197 198 pinctrl_gem3_default: gem3-default { 199 conf { 200 groups = "ethernet3_0_grp"; 201 slew-rate = <SLEW_RATE_SLOW>; 202 power-source = <IO_STANDARD_LVCMOS18>; 203 }; 204 205 conf-rx { 206 pins = "MIO70", "MIO72", "MIO74"; 207 bias-high-impedance; 208 low-power-disable; 209 }; 210 211 conf-bootstrap { 212 pins = "MIO71", "MIO73", "MIO75"; 213 bias-disable; 214 low-power-disable; 215 }; 216 217 conf-tx { 218 pins = "MIO64", "MIO65", "MIO66", 219 "MIO67", "MIO68", "MIO69"; 220 bias-disable; 221 low-power-enable; 222 }; 223 224 conf-mdio { 225 groups = "mdio3_0_grp"; 226 slew-rate = <SLEW_RATE_SLOW>; 227 power-source = <IO_STANDARD_LVCMOS18>; 228 bias-disable; 229 }; 230 231 mux-mdio { 232 function = "mdio3"; 233 groups = "mdio3_0_grp"; 234 }; 235 236 mux { 237 function = "ethernet3"; 238 groups = "ethernet3_0_grp"; 239 }; 240 }; 241 242 pinctrl_usb0_default: usb0-default { 243 conf { 244 groups = "usb0_0_grp"; 245 slew-rate = <SLEW_RATE_SLOW>; 246 power-source = <IO_STANDARD_LVCMOS18>; 247 }; 248 249 conf-rx { 250 pins = "MIO52", "MIO53", "MIO55"; 251 bias-high-impedance; 252 }; 253 254 conf-tx { 255 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 256 "MIO60", "MIO61", "MIO62", "MIO63"; 257 bias-disable; 258 }; 259 260 mux { 261 groups = "usb0_0_grp"; 262 function = "usb0"; 263 }; 264 }; 265 266 pinctrl_sdhci1_default: sdhci1-default { 267 conf { 268 groups = "sdio1_0_grp"; 269 slew-rate = <SLEW_RATE_SLOW>; 270 power-source = <IO_STANDARD_LVCMOS18>; 271 bias-disable; 272 }; 273 274 conf-cd { 275 groups = "sdio1_cd_0_grp"; 276 bias-high-impedance; 277 bias-pull-up; 278 slew-rate = <SLEW_RATE_SLOW>; 279 power-source = <IO_STANDARD_LVCMOS18>; 280 }; 281 282 mux-cd { 283 groups = "sdio1_cd_0_grp"; 284 function = "sdio1_cd"; 285 }; 286 287 mux { 288 groups = "sdio1_0_grp"; 289 function = "sdio1"; 290 }; 291 }; 292}; 293 294&uart1 { 295 status = "okay"; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_uart1_default>; 298}; 299