xref: /freebsd/sys/contrib/device-tree/src/arm64/xilinx/zynqmp-clk-ccf.dtsi (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
11/ {
12	pss_ref_clk: pss_ref_clk {
13		compatible = "fixed-clock";
14		#clock-cells = <0>;
15		clock-frequency = <33333333>;
16	};
17
18	video_clk: video_clk {
19		compatible = "fixed-clock";
20		#clock-cells = <0>;
21		clock-frequency = <27000000>;
22	};
23
24	pss_alt_ref_clk: pss_alt_ref_clk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <0>;
28	};
29
30	gt_crx_ref_clk: gt_crx_ref_clk {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <108000000>;
34	};
35
36	aux_ref_clk: aux_ref_clk {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-frequency = <27000000>;
40	};
41};
42
43&zynqmp_firmware {
44	zynqmp_clk: clock-controller {
45		#clock-cells = <1>;
46		compatible = "xlnx,zynqmp-clk";
47		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
48			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
49		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
50			      "aux_ref_clk", "gt_crx_ref_clk";
51	};
52};
53
54&can0 {
55	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
56};
57
58&can1 {
59	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
60};
61
62&cpu0 {
63	clocks = <&zynqmp_clk ACPU>;
64};
65
66&fpd_dma_chan1 {
67	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
68};
69
70&fpd_dma_chan2 {
71	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
72};
73
74&fpd_dma_chan3 {
75	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
76};
77
78&fpd_dma_chan4 {
79	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
80};
81
82&fpd_dma_chan5 {
83	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
84};
85
86&fpd_dma_chan6 {
87	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
88};
89
90&fpd_dma_chan7 {
91	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
92};
93
94&fpd_dma_chan8 {
95	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
96};
97
98&lpd_dma_chan1 {
99	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
100};
101
102&lpd_dma_chan2 {
103	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
104};
105
106&lpd_dma_chan3 {
107	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
108};
109
110&lpd_dma_chan4 {
111	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
112};
113
114&lpd_dma_chan5 {
115	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
116};
117
118&lpd_dma_chan6 {
119	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
120};
121
122&lpd_dma_chan7 {
123	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
124};
125
126&lpd_dma_chan8 {
127	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
128};
129
130&nand0 {
131	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
132};
133
134&gem0 {
135	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
136		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
137		 <&zynqmp_clk GEM_TSU>;
138	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
139};
140
141&gem1 {
142	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
143		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
144		 <&zynqmp_clk GEM_TSU>;
145	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
146};
147
148&gem2 {
149	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
150		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
151		 <&zynqmp_clk GEM_TSU>;
152	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
153};
154
155&gem3 {
156	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
157		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
158		 <&zynqmp_clk GEM_TSU>;
159	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
160};
161
162&gpio {
163	clocks = <&zynqmp_clk LPD_LSBUS>;
164};
165
166&i2c0 {
167	clocks = <&zynqmp_clk I2C0_REF>;
168};
169
170&i2c1 {
171	clocks = <&zynqmp_clk I2C1_REF>;
172};
173
174&pcie {
175	clocks = <&zynqmp_clk PCIE_REF>;
176};
177
178&qspi {
179	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
180};
181
182&sata {
183	clocks = <&zynqmp_clk SATA_REF>;
184};
185
186&sdhci0 {
187	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
188};
189
190&sdhci1 {
191	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
192};
193
194&spi0 {
195	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
196};
197
198&spi1 {
199	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
200};
201
202&ttc0 {
203	clocks = <&zynqmp_clk LPD_LSBUS>;
204};
205
206&ttc1 {
207	clocks = <&zynqmp_clk LPD_LSBUS>;
208};
209
210&ttc2 {
211	clocks = <&zynqmp_clk LPD_LSBUS>;
212};
213
214&ttc3 {
215	clocks = <&zynqmp_clk LPD_LSBUS>;
216};
217
218&uart0 {
219	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
220};
221
222&uart1 {
223	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
224};
225
226&dwc3_0 {
227	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
228};
229
230&dwc3_1 {
231	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
232};
233
234&watchdog0 {
235	clocks = <&zynqmp_clk WDT>;
236};
237
238&lpd_watchdog {
239	clocks = <&zynqmp_clk LPD_WDT>;
240};
241
242&zynqmp_dpdma {
243	clocks = <&zynqmp_clk DPDMA_REF>;
244};
245
246&zynqmp_dpsub {
247	clocks = <&zynqmp_clk TOPSW_LSBUS>,
248		 <&zynqmp_clk DP_AUDIO_REF>,
249		 <&zynqmp_clk DP_VIDEO_REF>;
250};
251