1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Clock specification for Xilinx ZynqMP 4 * 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11#include <dt-bindings/clock/xlnx-zynqmp-clk.h> 12/ { 13 pss_ref_clk: pss_ref_clk { 14 bootph-all; 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <33333333>; 18 }; 19 20 video_clk: video_clk { 21 bootph-all; 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <27000000>; 25 }; 26 27 pss_alt_ref_clk: pss_alt_ref_clk { 28 bootph-all; 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 gt_crx_ref_clk: gt_crx_ref_clk { 35 bootph-all; 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <108000000>; 39 }; 40 41 aux_ref_clk: aux_ref_clk { 42 bootph-all; 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <27000000>; 46 }; 47}; 48 49&zynqmp_firmware { 50 zynqmp_clk: clock-controller { 51 bootph-all; 52 #clock-cells = <1>; 53 compatible = "xlnx,zynqmp-clk"; 54 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, 55 <&aux_ref_clk>, <>_crx_ref_clk>; 56 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", 57 "aux_ref_clk", "gt_crx_ref_clk"; 58 }; 59}; 60 61&can0 { 62 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; 63}; 64 65&can1 { 66 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; 67}; 68 69&cpu0 { 70 clocks = <&zynqmp_clk ACPU>; 71}; 72 73&fpd_dma_chan1 { 74 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 75}; 76 77&fpd_dma_chan2 { 78 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 79}; 80 81&fpd_dma_chan3 { 82 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 83}; 84 85&fpd_dma_chan4 { 86 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 87}; 88 89&fpd_dma_chan5 { 90 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 91}; 92 93&fpd_dma_chan6 { 94 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 95}; 96 97&fpd_dma_chan7 { 98 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 99}; 100 101&fpd_dma_chan8 { 102 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 103}; 104 105&gpu { 106 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; 107}; 108 109&lpd_dma_chan1 { 110 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 111}; 112 113&lpd_dma_chan2 { 114 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 115}; 116 117&lpd_dma_chan3 { 118 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 119}; 120 121&lpd_dma_chan4 { 122 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 123}; 124 125&lpd_dma_chan5 { 126 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 127}; 128 129&lpd_dma_chan6 { 130 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 131}; 132 133&lpd_dma_chan7 { 134 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 135}; 136 137&lpd_dma_chan8 { 138 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 139}; 140 141&nand0 { 142 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; 143}; 144 145&gem0 { 146 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, 147 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, 148 <&zynqmp_clk GEM_TSU>; 149 assigned-clocks = <&zynqmp_clk GEM_TSU>; 150}; 151 152&gem1 { 153 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, 154 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, 155 <&zynqmp_clk GEM_TSU>; 156 assigned-clocks = <&zynqmp_clk GEM_TSU>; 157}; 158 159&gem2 { 160 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, 161 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, 162 <&zynqmp_clk GEM_TSU>; 163 assigned-clocks = <&zynqmp_clk GEM_TSU>; 164}; 165 166&gem3 { 167 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, 168 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, 169 <&zynqmp_clk GEM_TSU>; 170 assigned-clocks = <&zynqmp_clk GEM_TSU>; 171}; 172 173&gpio { 174 clocks = <&zynqmp_clk LPD_LSBUS>; 175}; 176 177&i2c0 { 178 clocks = <&zynqmp_clk I2C0_REF>; 179}; 180 181&i2c1 { 182 clocks = <&zynqmp_clk I2C1_REF>; 183}; 184 185&pcie { 186 clocks = <&zynqmp_clk PCIE_REF>; 187}; 188 189&qspi { 190 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; 191}; 192 193&sata { 194 clocks = <&zynqmp_clk SATA_REF>; 195}; 196 197&sdhci0 { 198 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; 199 assigned-clocks = <&zynqmp_clk SDIO0_REF>; 200}; 201 202&sdhci1 { 203 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; 204 assigned-clocks = <&zynqmp_clk SDIO1_REF>; 205}; 206 207&spi0 { 208 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; 209}; 210 211&spi1 { 212 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; 213}; 214 215&ttc0 { 216 clocks = <&zynqmp_clk LPD_LSBUS>; 217}; 218 219&ttc1 { 220 clocks = <&zynqmp_clk LPD_LSBUS>; 221}; 222 223&ttc2 { 224 clocks = <&zynqmp_clk LPD_LSBUS>; 225}; 226 227&ttc3 { 228 clocks = <&zynqmp_clk LPD_LSBUS>; 229}; 230 231&uart0 { 232 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; 233}; 234 235&uart1 { 236 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; 237}; 238 239&dwc3_0 { 240 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; 241}; 242 243&dwc3_1 { 244 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; 245}; 246 247&watchdog0 { 248 clocks = <&zynqmp_clk WDT>; 249}; 250 251&lpd_watchdog { 252 clocks = <&zynqmp_clk LPD_WDT>; 253}; 254 255&xilinx_ams { 256 clocks = <&zynqmp_clk AMS_REF>; 257}; 258 259&zynqmp_dpdma { 260 clocks = <&zynqmp_clk DPDMA_REF>; 261 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ 262}; 263 264&zynqmp_dpsub { 265 clocks = <&zynqmp_clk TOPSW_LSBUS>, 266 <&zynqmp_clk DP_AUDIO_REF>, 267 <&zynqmp_clk DP_VIDEO_REF>; 268 assigned-clocks = <&zynqmp_clk DP_STC_REF>, 269 <&zynqmp_clk DP_AUDIO_REF>, 270 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ 271}; 272