xref: /freebsd/sys/contrib/device-tree/src/arm64/xilinx/zynqmp-clk-ccf.dtsi (revision 31ba4ce8898f9dfa5e7f054fdbc26e50a599a6e3) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
11/ {
12	pss_ref_clk: pss_ref_clk {
13		compatible = "fixed-clock";
14		#clock-cells = <0>;
15		clock-frequency = <33333333>;
16	};
17
18	video_clk: video_clk {
19		compatible = "fixed-clock";
20		#clock-cells = <0>;
21		clock-frequency = <27000000>;
22	};
23
24	pss_alt_ref_clk: pss_alt_ref_clk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <0>;
28	};
29
30	gt_crx_ref_clk: gt_crx_ref_clk {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <108000000>;
34	};
35
36	aux_ref_clk: aux_ref_clk {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-frequency = <27000000>;
40	};
41};
42
43&can0 {
44	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
45};
46
47&can1 {
48	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
49};
50
51&cpu0 {
52	clocks = <&zynqmp_clk ACPU>;
53};
54
55&fpd_dma_chan1 {
56	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
57};
58
59&fpd_dma_chan2 {
60	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
61};
62
63&fpd_dma_chan3 {
64	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
65};
66
67&fpd_dma_chan4 {
68	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
69};
70
71&fpd_dma_chan5 {
72	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
73};
74
75&fpd_dma_chan6 {
76	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
77};
78
79&fpd_dma_chan7 {
80	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
81};
82
83&fpd_dma_chan8 {
84	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
85};
86
87&lpd_dma_chan1 {
88	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
89};
90
91&lpd_dma_chan2 {
92	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
93};
94
95&lpd_dma_chan3 {
96	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
97};
98
99&lpd_dma_chan4 {
100	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
101};
102
103&lpd_dma_chan5 {
104	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
105};
106
107&lpd_dma_chan6 {
108	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
109};
110
111&lpd_dma_chan7 {
112	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
113};
114
115&lpd_dma_chan8 {
116	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
117};
118
119&nand0 {
120	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
121};
122
123&gem0 {
124	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
125		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
126		 <&zynqmp_clk GEM_TSU>;
127	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
128};
129
130&gem1 {
131	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
132		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
133		 <&zynqmp_clk GEM_TSU>;
134	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
135};
136
137&gem2 {
138	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
139		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
140		 <&zynqmp_clk GEM_TSU>;
141	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
142};
143
144&gem3 {
145	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
146		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
147		 <&zynqmp_clk GEM_TSU>;
148	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
149};
150
151&gpio {
152	clocks = <&zynqmp_clk LPD_LSBUS>;
153};
154
155&i2c0 {
156	clocks = <&zynqmp_clk I2C0_REF>;
157};
158
159&i2c1 {
160	clocks = <&zynqmp_clk I2C1_REF>;
161};
162
163&pcie {
164	clocks = <&zynqmp_clk PCIE_REF>;
165};
166
167&qspi {
168	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
169};
170
171&sata {
172	clocks = <&zynqmp_clk SATA_REF>;
173};
174
175&sdhci0 {
176	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
177};
178
179&sdhci1 {
180	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
181};
182
183&spi0 {
184	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
185};
186
187&spi1 {
188	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
189};
190
191&ttc0 {
192	clocks = <&zynqmp_clk LPD_LSBUS>;
193};
194
195&ttc1 {
196	clocks = <&zynqmp_clk LPD_LSBUS>;
197};
198
199&ttc2 {
200	clocks = <&zynqmp_clk LPD_LSBUS>;
201};
202
203&ttc3 {
204	clocks = <&zynqmp_clk LPD_LSBUS>;
205};
206
207&uart0 {
208	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
209};
210
211&uart1 {
212	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
213};
214
215&usb0 {
216	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
217};
218
219&usb1 {
220	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
221};
222
223&watchdog0 {
224	clocks = <&zynqmp_clk WDT>;
225};
226
227&lpd_watchdog {
228	clocks = <&zynqmp_clk LPD_WDT>;
229};
230
231&zynqmp_dpdma {
232	clocks = <&zynqmp_clk DPDMA_REF>;
233};
234
235&zynqmp_dpsub {
236	clocks = <&zynqmp_clk TOPSW_LSBUS>,
237		 <&zynqmp_clk DP_AUDIO_REF>,
238		 <&zynqmp_clk DP_VIDEO_REF>;
239};
240