1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 msmc_ram: sram@70000000 { 25 compatible = "mmio-sram"; 26 reg = <0x00 0x70000000 0x00 0x800000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x00 0x00 0x70000000 0x800000>; 30 31 atf-sram@0 { 32 reg = <0x00 0x20000>; 33 }; 34 35 tifs-sram@1f0000 { 36 reg = <0x1f0000 0x10000>; 37 }; 38 39 l3cache-sram@200000 { 40 reg = <0x200000 0x200000>; 41 }; 42 }; 43 44 scm_conf: bus@100000 { 45 compatible = "simple-bus"; 46 reg = <0x00 0x00100000 0x00 0x1c000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x1c000>; 50 51 serdes_ln_ctrl: mux-controller@4080 { 52 compatible = "reg-mux"; 53 reg = <0x00004080 0x30>; 54 #mux-control-cells = <1>; 55 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 56 <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ 57 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 58 <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ 59 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 60 <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ 61 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 62 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 63 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 64 <J784S4_SERDES0_LANE3_USB>, 65 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 66 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 67 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 68 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 69 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 70 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 71 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 72 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 73 <J784S4_SERDES4_LANE0_EDP_LANE0>, 74 <J784S4_SERDES4_LANE1_EDP_LANE1>, 75 <J784S4_SERDES4_LANE2_EDP_LANE2>, 76 <J784S4_SERDES4_LANE3_EDP_LANE3>; 77 }; 78 }; 79 80 gic500: interrupt-controller@1800000 { 81 compatible = "arm,gic-v3"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 #interrupt-cells = <3>; 86 interrupt-controller; 87 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 88 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 89 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 90 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 91 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 92 93 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 94 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 95 96 gic_its: msi-controller@1820000 { 97 compatible = "arm,gic-v3-its"; 98 reg = <0x00 0x01820000 0x00 0x10000>; 99 socionext,synquacer-pre-its = <0x1000000 0x400000>; 100 msi-controller; 101 #msi-cells = <1>; 102 }; 103 }; 104 105 main_gpio_intr: interrupt-controller@a00000 { 106 compatible = "ti,sci-intr"; 107 reg = <0x00 0x00a00000 0x00 0x800>; 108 ti,intr-trigger-type = <1>; 109 interrupt-controller; 110 interrupt-parent = <&gic500>; 111 #interrupt-cells = <1>; 112 ti,sci = <&sms>; 113 ti,sci-dev-id = <10>; 114 ti,interrupt-ranges = <8 392 56>; 115 }; 116 117 main_pmx0: pinctrl@11c000 { 118 compatible = "pinctrl-single"; 119 /* Proxy 0 addressing */ 120 reg = <0x00 0x11c000 0x00 0x120>; 121 #pinctrl-cells = <1>; 122 pinctrl-single,register-width = <32>; 123 pinctrl-single,function-mask = <0xffffffff>; 124 }; 125 126 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 127 main_timerio_input: pinctrl@104200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x104200 0x00 0x50>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x00000007>; 133 }; 134 135 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 136 main_timerio_output: pinctrl@104280 { 137 compatible = "pinctrl-single"; 138 reg = <0x00 0x104280 0x00 0x20>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001f>; 142 }; 143 144 main_crypto: crypto@4e00000 { 145 compatible = "ti,j721e-sa2ul"; 146 reg = <0x00 0x4e00000 0x00 0x1200>; 147 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 151 152 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 153 <&main_udmap 0x4a41>; 154 dma-names = "tx", "rx1", "rx2"; 155 156 rng: rng@4e10000 { 157 compatible = "inside-secure,safexcel-eip76"; 158 reg = <0x00 0x4e10000 0x00 0x7d>; 159 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 main_timer0: timer@2400000 { 164 compatible = "ti,am654-timer"; 165 reg = <0x00 0x2400000 0x00 0x400>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&k3_clks 97 2>; 168 clock-names = "fck"; 169 assigned-clocks = <&k3_clks 97 2>; 170 assigned-clock-parents = <&k3_clks 97 3>; 171 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 172 ti,timer-pwm; 173 }; 174 175 main_timer1: timer@2410000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x2410000 0x00 0x400>; 178 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&k3_clks 98 2>; 180 clock-names = "fck"; 181 assigned-clocks = <&k3_clks 98 2>; 182 assigned-clock-parents = <&k3_clks 98 3>; 183 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 184 ti,timer-pwm; 185 }; 186 187 main_timer2: timer@2420000 { 188 compatible = "ti,am654-timer"; 189 reg = <0x00 0x2420000 0x00 0x400>; 190 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&k3_clks 99 2>; 192 clock-names = "fck"; 193 assigned-clocks = <&k3_clks 99 2>; 194 assigned-clock-parents = <&k3_clks 99 3>; 195 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 196 ti,timer-pwm; 197 }; 198 199 main_timer3: timer@2430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x2430000 0x00 0x400>; 202 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 100 2>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 100 2>; 206 assigned-clock-parents = <&k3_clks 100 3>; 207 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 }; 210 211 main_timer4: timer@2440000 { 212 compatible = "ti,am654-timer"; 213 reg = <0x00 0x2440000 0x00 0x400>; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&k3_clks 101 2>; 216 clock-names = "fck"; 217 assigned-clocks = <&k3_clks 101 2>; 218 assigned-clock-parents = <&k3_clks 101 3>; 219 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 220 ti,timer-pwm; 221 }; 222 223 main_timer5: timer@2450000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2450000 0x00 0x400>; 226 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 102 2>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 102 2>; 230 assigned-clock-parents = <&k3_clks 102 3>; 231 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer6: timer@2460000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2460000 0x00 0x400>; 238 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 103 2>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 103 2>; 242 assigned-clock-parents = <&k3_clks 103 3>; 243 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer7: timer@2470000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2470000 0x00 0x400>; 250 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 104 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 104 2>; 254 assigned-clock-parents = <&k3_clks 104 3>; 255 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer8: timer@2480000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2480000 0x00 0x400>; 262 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 105 2>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 105 2>; 266 assigned-clock-parents = <&k3_clks 105 3>; 267 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer9: timer@2490000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2490000 0x00 0x400>; 274 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 106 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 106 2>; 278 assigned-clock-parents = <&k3_clks 106 3>; 279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer10: timer@24a0000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x24a0000 0x00 0x400>; 286 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 107 2>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 107 2>; 290 assigned-clock-parents = <&k3_clks 107 3>; 291 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer11: timer@24b0000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x24b0000 0x00 0x400>; 298 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 108 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 108 2>; 302 assigned-clock-parents = <&k3_clks 108 3>; 303 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer12: timer@24c0000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x24c0000 0x00 0x400>; 310 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 109 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 109 2>; 314 assigned-clock-parents = <&k3_clks 109 3>; 315 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer13: timer@24d0000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x24d0000 0x00 0x400>; 322 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 110 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 110 2>; 326 assigned-clock-parents = <&k3_clks 110 3>; 327 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer14: timer@24e0000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x24e0000 0x00 0x400>; 334 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 111 2>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 111 2>; 338 assigned-clock-parents = <&k3_clks 111 3>; 339 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer15: timer@24f0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24f0000 0x00 0x400>; 346 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 112 2>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 112 2>; 350 assigned-clock-parents = <&k3_clks 112 3>; 351 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer16: timer@2500000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x2500000 0x00 0x400>; 358 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 113 2>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 113 2>; 362 assigned-clock-parents = <&k3_clks 113 3>; 363 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer17: timer@2510000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x2510000 0x00 0x400>; 370 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 114 2>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 114 2>; 374 assigned-clock-parents = <&k3_clks 114 3>; 375 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer18: timer@2520000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x2520000 0x00 0x400>; 382 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 115 2>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 115 2>; 386 assigned-clock-parents = <&k3_clks 115 3>; 387 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_timer19: timer@2530000 { 392 compatible = "ti,am654-timer"; 393 reg = <0x00 0x2530000 0x00 0x400>; 394 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&k3_clks 116 2>; 396 clock-names = "fck"; 397 assigned-clocks = <&k3_clks 116 2>; 398 assigned-clock-parents = <&k3_clks 116 3>; 399 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 400 ti,timer-pwm; 401 }; 402 403 main_uart0: serial@2800000 { 404 compatible = "ti,j721e-uart", "ti,am654-uart"; 405 reg = <0x00 0x02800000 0x00 0x200>; 406 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 407 current-speed = <115200>; 408 clocks = <&k3_clks 146 0>; 409 clock-names = "fclk"; 410 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 411 status = "disabled"; 412 }; 413 414 main_uart1: serial@2810000 { 415 compatible = "ti,j721e-uart", "ti,am654-uart"; 416 reg = <0x00 0x02810000 0x00 0x200>; 417 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 418 current-speed = <115200>; 419 clocks = <&k3_clks 388 0>; 420 clock-names = "fclk"; 421 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 422 status = "disabled"; 423 }; 424 425 main_uart2: serial@2820000 { 426 compatible = "ti,j721e-uart", "ti,am654-uart"; 427 reg = <0x00 0x02820000 0x00 0x200>; 428 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 429 current-speed = <115200>; 430 clocks = <&k3_clks 389 0>; 431 clock-names = "fclk"; 432 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 433 status = "disabled"; 434 }; 435 436 main_uart3: serial@2830000 { 437 compatible = "ti,j721e-uart", "ti,am654-uart"; 438 reg = <0x00 0x02830000 0x00 0x200>; 439 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 440 current-speed = <115200>; 441 clocks = <&k3_clks 390 0>; 442 clock-names = "fclk"; 443 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 444 status = "disabled"; 445 }; 446 447 main_uart4: serial@2840000 { 448 compatible = "ti,j721e-uart", "ti,am654-uart"; 449 reg = <0x00 0x02840000 0x00 0x200>; 450 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 451 current-speed = <115200>; 452 clocks = <&k3_clks 391 0>; 453 clock-names = "fclk"; 454 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 455 status = "disabled"; 456 }; 457 458 main_uart5: serial@2850000 { 459 compatible = "ti,j721e-uart", "ti,am654-uart"; 460 reg = <0x00 0x02850000 0x00 0x200>; 461 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 462 current-speed = <115200>; 463 clocks = <&k3_clks 392 0>; 464 clock-names = "fclk"; 465 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 466 status = "disabled"; 467 }; 468 469 main_uart6: serial@2860000 { 470 compatible = "ti,j721e-uart", "ti,am654-uart"; 471 reg = <0x00 0x02860000 0x00 0x200>; 472 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 473 current-speed = <115200>; 474 clocks = <&k3_clks 393 0>; 475 clock-names = "fclk"; 476 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 477 status = "disabled"; 478 }; 479 480 main_uart7: serial@2870000 { 481 compatible = "ti,j721e-uart", "ti,am654-uart"; 482 reg = <0x00 0x02870000 0x00 0x200>; 483 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 484 current-speed = <115200>; 485 clocks = <&k3_clks 394 0>; 486 clock-names = "fclk"; 487 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 488 status = "disabled"; 489 }; 490 491 main_uart8: serial@2880000 { 492 compatible = "ti,j721e-uart", "ti,am654-uart"; 493 reg = <0x00 0x02880000 0x00 0x200>; 494 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 495 current-speed = <115200>; 496 clocks = <&k3_clks 395 0>; 497 clock-names = "fclk"; 498 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 499 status = "disabled"; 500 }; 501 502 main_uart9: serial@2890000 { 503 compatible = "ti,j721e-uart", "ti,am654-uart"; 504 reg = <0x00 0x02890000 0x00 0x200>; 505 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 506 current-speed = <115200>; 507 clocks = <&k3_clks 396 0>; 508 clock-names = "fclk"; 509 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 510 status = "disabled"; 511 }; 512 513 main_gpio0: gpio@600000 { 514 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 515 reg = <0x00 0x00600000 0x00 0x100>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-parent = <&main_gpio_intr>; 519 interrupts = <145>, <146>, <147>, <148>, <149>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 ti,ngpio = <66>; 523 ti,davinci-gpio-unbanked = <0>; 524 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 525 clocks = <&k3_clks 163 0>; 526 clock-names = "gpio"; 527 status = "disabled"; 528 }; 529 530 main_gpio2: gpio@610000 { 531 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 532 reg = <0x00 0x00610000 0x00 0x100>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-parent = <&main_gpio_intr>; 536 interrupts = <154>, <155>, <156>, <157>, <158>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 ti,ngpio = <66>; 540 ti,davinci-gpio-unbanked = <0>; 541 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 542 clocks = <&k3_clks 164 0>; 543 clock-names = "gpio"; 544 status = "disabled"; 545 }; 546 547 main_gpio4: gpio@620000 { 548 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 549 reg = <0x00 0x00620000 0x00 0x100>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-parent = <&main_gpio_intr>; 553 interrupts = <163>, <164>, <165>, <166>, <167>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ti,ngpio = <66>; 557 ti,davinci-gpio-unbanked = <0>; 558 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 165 0>; 560 clock-names = "gpio"; 561 status = "disabled"; 562 }; 563 564 main_gpio6: gpio@630000 { 565 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 566 reg = <0x00 0x00630000 0x00 0x100>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 interrupt-parent = <&main_gpio_intr>; 570 interrupts = <172>, <173>, <174>, <175>, <176>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 ti,ngpio = <66>; 574 ti,davinci-gpio-unbanked = <0>; 575 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 166 0>; 577 clock-names = "gpio"; 578 status = "disabled"; 579 }; 580 581 main_i2c0: i2c@2000000 { 582 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 583 reg = <0x00 0x02000000 0x00 0x100>; 584 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 clocks = <&k3_clks 270 2>; 588 clock-names = "fck"; 589 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 590 status = "disabled"; 591 }; 592 593 main_i2c1: i2c@2010000 { 594 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 595 reg = <0x00 0x02010000 0x00 0x100>; 596 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 clocks = <&k3_clks 271 2>; 600 clock-names = "fck"; 601 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 602 status = "disabled"; 603 }; 604 605 main_i2c2: i2c@2020000 { 606 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 607 reg = <0x00 0x02020000 0x00 0x100>; 608 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&k3_clks 272 2>; 612 clock-names = "fck"; 613 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 614 status = "disabled"; 615 }; 616 617 main_i2c3: i2c@2030000 { 618 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 619 reg = <0x00 0x02030000 0x00 0x100>; 620 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 clocks = <&k3_clks 273 2>; 624 clock-names = "fck"; 625 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 626 status = "disabled"; 627 }; 628 629 main_i2c4: i2c@2040000 { 630 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 631 reg = <0x00 0x02040000 0x00 0x100>; 632 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&k3_clks 274 2>; 636 clock-names = "fck"; 637 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 638 status = "disabled"; 639 }; 640 641 main_i2c5: i2c@2050000 { 642 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 643 reg = <0x00 0x02050000 0x00 0x100>; 644 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 clocks = <&k3_clks 275 2>; 648 clock-names = "fck"; 649 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 650 status = "disabled"; 651 }; 652 653 main_i2c6: i2c@2060000 { 654 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 655 reg = <0x00 0x02060000 0x00 0x100>; 656 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&k3_clks 276 2>; 660 clock-names = "fck"; 661 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 662 status = "disabled"; 663 }; 664 665 main_sdhci0: mmc@4f80000 { 666 compatible = "ti,j721e-sdhci-8bit"; 667 reg = <0x00 0x04f80000 0x00 0x1000>, 668 <0x00 0x04f88000 0x00 0x400>; 669 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 670 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 671 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 672 clock-names = "clk_ahb", "clk_xin"; 673 assigned-clocks = <&k3_clks 140 2>; 674 assigned-clock-parents = <&k3_clks 140 3>; 675 bus-width = <8>; 676 ti,otap-del-sel-legacy = <0x0>; 677 ti,otap-del-sel-mmc-hs = <0x0>; 678 ti,otap-del-sel-ddr52 = <0x6>; 679 ti,otap-del-sel-hs200 = <0x8>; 680 ti,otap-del-sel-hs400 = <0x5>; 681 ti,itap-del-sel-legacy = <0x10>; 682 ti,itap-del-sel-mmc-hs = <0xa>; 683 ti,strobe-sel = <0x77>; 684 ti,clkbuf-sel = <0x7>; 685 ti,trm-icp = <0x8>; 686 mmc-ddr-1_8v; 687 mmc-hs200-1_8v; 688 mmc-hs400-1_8v; 689 dma-coherent; 690 status = "disabled"; 691 }; 692 693 main_sdhci1: mmc@4fb0000 { 694 compatible = "ti,j721e-sdhci-4bit"; 695 reg = <0x00 0x04fb0000 0x00 0x1000>, 696 <0x00 0x04fb8000 0x00 0x400>; 697 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 698 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 699 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 700 clock-names = "clk_ahb", "clk_xin"; 701 assigned-clocks = <&k3_clks 141 4>; 702 assigned-clock-parents = <&k3_clks 141 5>; 703 bus-width = <4>; 704 ti,otap-del-sel-legacy = <0x0>; 705 ti,otap-del-sel-sd-hs = <0x0>; 706 ti,otap-del-sel-sdr12 = <0xf>; 707 ti,otap-del-sel-sdr25 = <0xf>; 708 ti,otap-del-sel-sdr50 = <0xc>; 709 ti,otap-del-sel-sdr104 = <0x5>; 710 ti,otap-del-sel-ddr50 = <0xc>; 711 ti,itap-del-sel-legacy = <0x0>; 712 ti,itap-del-sel-sd-hs = <0x0>; 713 ti,itap-del-sel-sdr12 = <0x0>; 714 ti,itap-del-sel-sdr25 = <0x0>; 715 ti,itap-del-sel-ddr50 = <0x2>; 716 ti,clkbuf-sel = <0x7>; 717 ti,trm-icp = <0x8>; 718 dma-coherent; 719 sdhci-caps-mask = <0x00000003 0x00000000>; 720 no-1-8-v; 721 status = "disabled"; 722 }; 723 724 serdes_wiz0: wiz@5060000 { 725 compatible = "ti,j784s4-wiz-10g"; 726 #address-cells = <1>; 727 #size-cells = <1>; 728 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 729 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 730 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 731 assigned-clocks = <&k3_clks 404 6>; 732 assigned-clock-parents = <&k3_clks 404 10>; 733 num-lanes = <4>; 734 #reset-cells = <1>; 735 #clock-cells = <1>; 736 ranges = <0x5060000 0x00 0x5060000 0x10000>; 737 status = "disabled"; 738 739 serdes0: serdes@5060000 { 740 compatible = "ti,j721e-serdes-10g"; 741 reg = <0x05060000 0x010000>; 742 reg-names = "torrent_phy"; 743 resets = <&serdes_wiz0 0>; 744 reset-names = "torrent_reset"; 745 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 746 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 747 clock-names = "refclk", "phy_en_refclk"; 748 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 749 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 750 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 751 assigned-clock-parents = <&k3_clks 404 6>, 752 <&k3_clks 404 6>, 753 <&k3_clks 404 6>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 #clock-cells = <1>; 757 status = "disabled"; 758 }; 759 }; 760 761 serdes_wiz1: wiz@5070000 { 762 compatible = "ti,j784s4-wiz-10g"; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 766 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 767 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 768 assigned-clocks = <&k3_clks 405 6>; 769 assigned-clock-parents = <&k3_clks 405 10>; 770 num-lanes = <4>; 771 #reset-cells = <1>; 772 #clock-cells = <1>; 773 ranges = <0x05070000 0x00 0x05070000 0x10000>; 774 status = "disabled"; 775 776 serdes1: serdes@5070000 { 777 compatible = "ti,j721e-serdes-10g"; 778 reg = <0x05070000 0x010000>; 779 reg-names = "torrent_phy"; 780 resets = <&serdes_wiz1 0>; 781 reset-names = "torrent_reset"; 782 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 783 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 784 clock-names = "refclk", "phy_en_refclk"; 785 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 786 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 787 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 788 assigned-clock-parents = <&k3_clks 405 6>, 789 <&k3_clks 405 6>, 790 <&k3_clks 405 6>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 #clock-cells = <1>; 794 status = "disabled"; 795 }; 796 }; 797 798 serdes_wiz2: wiz@5020000 { 799 compatible = "ti,j784s4-wiz-10g"; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 803 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 804 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 805 assigned-clocks = <&k3_clks 406 6>; 806 assigned-clock-parents = <&k3_clks 406 10>; 807 num-lanes = <4>; 808 #reset-cells = <1>; 809 #clock-cells = <1>; 810 ranges = <0x05020000 0x00 0x05020000 0x10000>; 811 status = "disabled"; 812 813 serdes2: serdes@5020000 { 814 compatible = "ti,j721e-serdes-10g"; 815 reg = <0x05020000 0x010000>; 816 reg-names = "torrent_phy"; 817 resets = <&serdes_wiz2 0>; 818 reset-names = "torrent_reset"; 819 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 820 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 821 clock-names = "refclk", "phy_en_refclk"; 822 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 823 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 824 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 825 assigned-clock-parents = <&k3_clks 406 6>, 826 <&k3_clks 406 6>, 827 <&k3_clks 406 6>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 #clock-cells = <1>; 831 status = "disabled"; 832 }; 833 }; 834 835 serdes_wiz4: wiz@5050000 { 836 compatible = "ti,j784s4-wiz-10g"; 837 #address-cells = <1>; 838 #size-cells = <1>; 839 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 840 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 841 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 842 assigned-clocks = <&k3_clks 407 6>; 843 assigned-clock-parents = <&k3_clks 407 10>; 844 num-lanes = <4>; 845 #reset-cells = <1>; 846 #clock-cells = <1>; 847 ranges = <0x05050000 0x00 0x05050000 0x10000>, 848 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 849 status = "disabled"; 850 851 serdes4: serdes@5050000 { 852 /* 853 * Note: we also map DPTX PHY registers as the Torrent 854 * needs to manage those. 855 */ 856 compatible = "ti,j721e-serdes-10g"; 857 reg = <0x05050000 0x010000>, 858 <0x0a030a00 0x40>; /* DPTX PHY */ 859 reg-names = "torrent_phy"; 860 resets = <&serdes_wiz4 0>; 861 reset-names = "torrent_reset"; 862 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 863 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 864 clock-names = "refclk", "phy_en_refclk"; 865 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 866 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 867 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 868 assigned-clock-parents = <&k3_clks 407 6>, 869 <&k3_clks 407 6>, 870 <&k3_clks 407 6>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 #clock-cells = <1>; 874 status = "disabled"; 875 }; 876 }; 877 878 main_navss: bus@30000000 { 879 bootph-all; 880 compatible = "simple-bus"; 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 884 ti,sci-dev-id = <280>; 885 dma-coherent; 886 dma-ranges; 887 888 main_navss_intr: interrupt-controller@310e0000 { 889 compatible = "ti,sci-intr"; 890 reg = <0x00 0x310e0000 0x00 0x4000>; 891 ti,intr-trigger-type = <4>; 892 interrupt-controller; 893 interrupt-parent = <&gic500>; 894 #interrupt-cells = <1>; 895 ti,sci = <&sms>; 896 ti,sci-dev-id = <283>; 897 ti,interrupt-ranges = <0 64 64>, 898 <64 448 64>, 899 <128 672 64>; 900 }; 901 902 main_udmass_inta: msi-controller@33d00000 { 903 compatible = "ti,sci-inta"; 904 reg = <0x00 0x33d00000 0x00 0x100000>; 905 interrupt-controller; 906 #interrupt-cells = <0>; 907 interrupt-parent = <&main_navss_intr>; 908 msi-controller; 909 ti,sci = <&sms>; 910 ti,sci-dev-id = <321>; 911 ti,interrupt-ranges = <0 0 256>; 912 ti,unmapped-event-sources = <&main_bcdma_csi>; 913 }; 914 915 secure_proxy_main: mailbox@32c00000 { 916 bootph-all; 917 compatible = "ti,am654-secure-proxy"; 918 #mbox-cells = <1>; 919 reg-names = "target_data", "rt", "scfg"; 920 reg = <0x00 0x32c00000 0x00 0x100000>, 921 <0x00 0x32400000 0x00 0x100000>, 922 <0x00 0x32800000 0x00 0x100000>; 923 interrupt-names = "rx_011"; 924 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 925 }; 926 927 hwspinlock: hwlock@30e00000 { 928 compatible = "ti,am654-hwspinlock"; 929 reg = <0x00 0x30e00000 0x00 0x1000>; 930 #hwlock-cells = <1>; 931 }; 932 933 mailbox0_cluster0: mailbox@31f80000 { 934 compatible = "ti,am654-mailbox"; 935 reg = <0x00 0x31f80000 0x00 0x200>; 936 #mbox-cells = <1>; 937 ti,mbox-num-users = <4>; 938 ti,mbox-num-fifos = <16>; 939 interrupt-parent = <&main_navss_intr>; 940 status = "disabled"; 941 }; 942 943 mailbox0_cluster1: mailbox@31f81000 { 944 compatible = "ti,am654-mailbox"; 945 reg = <0x00 0x31f81000 0x00 0x200>; 946 #mbox-cells = <1>; 947 ti,mbox-num-users = <4>; 948 ti,mbox-num-fifos = <16>; 949 interrupt-parent = <&main_navss_intr>; 950 status = "disabled"; 951 }; 952 953 mailbox0_cluster2: mailbox@31f82000 { 954 compatible = "ti,am654-mailbox"; 955 reg = <0x00 0x31f82000 0x00 0x200>; 956 #mbox-cells = <1>; 957 ti,mbox-num-users = <4>; 958 ti,mbox-num-fifos = <16>; 959 interrupt-parent = <&main_navss_intr>; 960 status = "disabled"; 961 }; 962 963 mailbox0_cluster3: mailbox@31f83000 { 964 compatible = "ti,am654-mailbox"; 965 reg = <0x00 0x31f83000 0x00 0x200>; 966 #mbox-cells = <1>; 967 ti,mbox-num-users = <4>; 968 ti,mbox-num-fifos = <16>; 969 interrupt-parent = <&main_navss_intr>; 970 status = "disabled"; 971 }; 972 973 mailbox0_cluster4: mailbox@31f84000 { 974 compatible = "ti,am654-mailbox"; 975 reg = <0x00 0x31f84000 0x00 0x200>; 976 #mbox-cells = <1>; 977 ti,mbox-num-users = <4>; 978 ti,mbox-num-fifos = <16>; 979 interrupt-parent = <&main_navss_intr>; 980 status = "disabled"; 981 }; 982 983 mailbox0_cluster5: mailbox@31f85000 { 984 compatible = "ti,am654-mailbox"; 985 reg = <0x00 0x31f85000 0x00 0x200>; 986 #mbox-cells = <1>; 987 ti,mbox-num-users = <4>; 988 ti,mbox-num-fifos = <16>; 989 interrupt-parent = <&main_navss_intr>; 990 status = "disabled"; 991 }; 992 993 mailbox0_cluster6: mailbox@31f86000 { 994 compatible = "ti,am654-mailbox"; 995 reg = <0x00 0x31f86000 0x00 0x200>; 996 #mbox-cells = <1>; 997 ti,mbox-num-users = <4>; 998 ti,mbox-num-fifos = <16>; 999 interrupt-parent = <&main_navss_intr>; 1000 status = "disabled"; 1001 }; 1002 1003 mailbox0_cluster7: mailbox@31f87000 { 1004 compatible = "ti,am654-mailbox"; 1005 reg = <0x00 0x31f87000 0x00 0x200>; 1006 #mbox-cells = <1>; 1007 ti,mbox-num-users = <4>; 1008 ti,mbox-num-fifos = <16>; 1009 interrupt-parent = <&main_navss_intr>; 1010 status = "disabled"; 1011 }; 1012 1013 mailbox0_cluster8: mailbox@31f88000 { 1014 compatible = "ti,am654-mailbox"; 1015 reg = <0x00 0x31f88000 0x00 0x200>; 1016 #mbox-cells = <1>; 1017 ti,mbox-num-users = <4>; 1018 ti,mbox-num-fifos = <16>; 1019 interrupt-parent = <&main_navss_intr>; 1020 status = "disabled"; 1021 }; 1022 1023 mailbox0_cluster9: mailbox@31f89000 { 1024 compatible = "ti,am654-mailbox"; 1025 reg = <0x00 0x31f89000 0x00 0x200>; 1026 #mbox-cells = <1>; 1027 ti,mbox-num-users = <4>; 1028 ti,mbox-num-fifos = <16>; 1029 interrupt-parent = <&main_navss_intr>; 1030 status = "disabled"; 1031 }; 1032 1033 mailbox0_cluster10: mailbox@31f8a000 { 1034 compatible = "ti,am654-mailbox"; 1035 reg = <0x00 0x31f8a000 0x00 0x200>; 1036 #mbox-cells = <1>; 1037 ti,mbox-num-users = <4>; 1038 ti,mbox-num-fifos = <16>; 1039 interrupt-parent = <&main_navss_intr>; 1040 status = "disabled"; 1041 }; 1042 1043 mailbox0_cluster11: mailbox@31f8b000 { 1044 compatible = "ti,am654-mailbox"; 1045 reg = <0x00 0x31f8b000 0x00 0x200>; 1046 #mbox-cells = <1>; 1047 ti,mbox-num-users = <4>; 1048 ti,mbox-num-fifos = <16>; 1049 interrupt-parent = <&main_navss_intr>; 1050 status = "disabled"; 1051 }; 1052 1053 mailbox1_cluster0: mailbox@31f90000 { 1054 compatible = "ti,am654-mailbox"; 1055 reg = <0x00 0x31f90000 0x00 0x200>; 1056 #mbox-cells = <1>; 1057 ti,mbox-num-users = <4>; 1058 ti,mbox-num-fifos = <16>; 1059 interrupt-parent = <&main_navss_intr>; 1060 status = "disabled"; 1061 }; 1062 1063 mailbox1_cluster1: mailbox@31f91000 { 1064 compatible = "ti,am654-mailbox"; 1065 reg = <0x00 0x31f91000 0x00 0x200>; 1066 #mbox-cells = <1>; 1067 ti,mbox-num-users = <4>; 1068 ti,mbox-num-fifos = <16>; 1069 interrupt-parent = <&main_navss_intr>; 1070 status = "disabled"; 1071 }; 1072 1073 mailbox1_cluster2: mailbox@31f92000 { 1074 compatible = "ti,am654-mailbox"; 1075 reg = <0x00 0x31f92000 0x00 0x200>; 1076 #mbox-cells = <1>; 1077 ti,mbox-num-users = <4>; 1078 ti,mbox-num-fifos = <16>; 1079 interrupt-parent = <&main_navss_intr>; 1080 status = "disabled"; 1081 }; 1082 1083 mailbox1_cluster3: mailbox@31f93000 { 1084 compatible = "ti,am654-mailbox"; 1085 reg = <0x00 0x31f93000 0x00 0x200>; 1086 #mbox-cells = <1>; 1087 ti,mbox-num-users = <4>; 1088 ti,mbox-num-fifos = <16>; 1089 interrupt-parent = <&main_navss_intr>; 1090 status = "disabled"; 1091 }; 1092 1093 mailbox1_cluster4: mailbox@31f94000 { 1094 compatible = "ti,am654-mailbox"; 1095 reg = <0x00 0x31f94000 0x00 0x200>; 1096 #mbox-cells = <1>; 1097 ti,mbox-num-users = <4>; 1098 ti,mbox-num-fifos = <16>; 1099 interrupt-parent = <&main_navss_intr>; 1100 status = "disabled"; 1101 }; 1102 1103 mailbox1_cluster5: mailbox@31f95000 { 1104 compatible = "ti,am654-mailbox"; 1105 reg = <0x00 0x31f95000 0x00 0x200>; 1106 #mbox-cells = <1>; 1107 ti,mbox-num-users = <4>; 1108 ti,mbox-num-fifos = <16>; 1109 interrupt-parent = <&main_navss_intr>; 1110 status = "disabled"; 1111 }; 1112 1113 mailbox1_cluster6: mailbox@31f96000 { 1114 compatible = "ti,am654-mailbox"; 1115 reg = <0x00 0x31f96000 0x00 0x200>; 1116 #mbox-cells = <1>; 1117 ti,mbox-num-users = <4>; 1118 ti,mbox-num-fifos = <16>; 1119 interrupt-parent = <&main_navss_intr>; 1120 status = "disabled"; 1121 }; 1122 1123 mailbox1_cluster7: mailbox@31f97000 { 1124 compatible = "ti,am654-mailbox"; 1125 reg = <0x00 0x31f97000 0x00 0x200>; 1126 #mbox-cells = <1>; 1127 ti,mbox-num-users = <4>; 1128 ti,mbox-num-fifos = <16>; 1129 interrupt-parent = <&main_navss_intr>; 1130 status = "disabled"; 1131 }; 1132 1133 mailbox1_cluster8: mailbox@31f98000 { 1134 compatible = "ti,am654-mailbox"; 1135 reg = <0x00 0x31f98000 0x00 0x200>; 1136 #mbox-cells = <1>; 1137 ti,mbox-num-users = <4>; 1138 ti,mbox-num-fifos = <16>; 1139 interrupt-parent = <&main_navss_intr>; 1140 status = "disabled"; 1141 }; 1142 1143 mailbox1_cluster9: mailbox@31f99000 { 1144 compatible = "ti,am654-mailbox"; 1145 reg = <0x00 0x31f99000 0x00 0x200>; 1146 #mbox-cells = <1>; 1147 ti,mbox-num-users = <4>; 1148 ti,mbox-num-fifos = <16>; 1149 interrupt-parent = <&main_navss_intr>; 1150 status = "disabled"; 1151 }; 1152 1153 mailbox1_cluster10: mailbox@31f9a000 { 1154 compatible = "ti,am654-mailbox"; 1155 reg = <0x00 0x31f9a000 0x00 0x200>; 1156 #mbox-cells = <1>; 1157 ti,mbox-num-users = <4>; 1158 ti,mbox-num-fifos = <16>; 1159 interrupt-parent = <&main_navss_intr>; 1160 status = "disabled"; 1161 }; 1162 1163 mailbox1_cluster11: mailbox@31f9b000 { 1164 compatible = "ti,am654-mailbox"; 1165 reg = <0x00 0x31f9b000 0x00 0x200>; 1166 #mbox-cells = <1>; 1167 ti,mbox-num-users = <4>; 1168 ti,mbox-num-fifos = <16>; 1169 interrupt-parent = <&main_navss_intr>; 1170 status = "disabled"; 1171 }; 1172 1173 main_ringacc: ringacc@3c000000 { 1174 compatible = "ti,am654-navss-ringacc"; 1175 reg = <0x00 0x3c000000 0x00 0x400000>, 1176 <0x00 0x38000000 0x00 0x400000>, 1177 <0x00 0x31120000 0x00 0x100>, 1178 <0x00 0x33000000 0x00 0x40000>, 1179 <0x00 0x31080000 0x00 0x40000>; 1180 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1181 ti,num-rings = <1024>; 1182 ti,sci-rm-range-gp-rings = <0x1>; 1183 ti,sci = <&sms>; 1184 ti,sci-dev-id = <315>; 1185 msi-parent = <&main_udmass_inta>; 1186 }; 1187 1188 main_udmap: dma-controller@31150000 { 1189 compatible = "ti,j721e-navss-main-udmap"; 1190 reg = <0x00 0x31150000 0x00 0x100>, 1191 <0x00 0x34000000 0x00 0x80000>, 1192 <0x00 0x35000000 0x00 0x200000>, 1193 <0x00 0x30b00000 0x00 0x20000>, 1194 <0x00 0x30c00000 0x00 0x8000>, 1195 <0x00 0x30d00000 0x00 0x4000>; 1196 reg-names = "gcfg", "rchanrt", "tchanrt", 1197 "tchan", "rchan", "rflow"; 1198 msi-parent = <&main_udmass_inta>; 1199 #dma-cells = <1>; 1200 1201 ti,sci = <&sms>; 1202 ti,sci-dev-id = <319>; 1203 ti,ringacc = <&main_ringacc>; 1204 1205 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1206 <0x0f>, /* TX_HCHAN */ 1207 <0x10>; /* TX_UHCHAN */ 1208 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1209 <0x0b>, /* RX_HCHAN */ 1210 <0x0c>; /* RX_UHCHAN */ 1211 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1212 }; 1213 1214 main_bcdma_csi: dma-controller@311a0000 { 1215 compatible = "ti,j721s2-dmss-bcdma-csi"; 1216 reg = <0x00 0x311a0000 0x00 0x100>, 1217 <0x00 0x35d00000 0x00 0x20000>, 1218 <0x00 0x35c00000 0x00 0x10000>, 1219 <0x00 0x35e00000 0x00 0x80000>; 1220 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1221 msi-parent = <&main_udmass_inta>; 1222 #dma-cells = <3>; 1223 ti,sci = <&sms>; 1224 ti,sci-dev-id = <281>; 1225 ti,sci-rm-range-rchan = <0x21>; 1226 ti,sci-rm-range-tchan = <0x22>; 1227 status = "disabled"; 1228 }; 1229 1230 cpts@310d0000 { 1231 compatible = "ti,j721e-cpts"; 1232 reg = <0x00 0x310d0000 0x00 0x400>; 1233 reg-names = "cpts"; 1234 clocks = <&k3_clks 282 0>; 1235 clock-names = "cpts"; 1236 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1237 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1238 interrupts-extended = <&main_navss_intr 391>; 1239 interrupt-names = "cpts"; 1240 ti,cpts-periodic-outputs = <6>; 1241 ti,cpts-ext-ts-inputs = <8>; 1242 }; 1243 }; 1244 1245 main_mcan0: can@2701000 { 1246 compatible = "bosch,m_can"; 1247 reg = <0x00 0x02701000 0x00 0x200>, 1248 <0x00 0x02708000 0x00 0x8000>; 1249 reg-names = "m_can", "message_ram"; 1250 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1251 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1252 clock-names = "hclk", "cclk"; 1253 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1255 interrupt-names = "int0", "int1"; 1256 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1257 status = "disabled"; 1258 }; 1259 1260 main_mcan1: can@2711000 { 1261 compatible = "bosch,m_can"; 1262 reg = <0x00 0x02711000 0x00 0x200>, 1263 <0x00 0x02718000 0x00 0x8000>; 1264 reg-names = "m_can", "message_ram"; 1265 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1266 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1267 clock-names = "hclk", "cclk"; 1268 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "int0", "int1"; 1271 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1272 status = "disabled"; 1273 }; 1274 1275 main_mcan2: can@2721000 { 1276 compatible = "bosch,m_can"; 1277 reg = <0x00 0x02721000 0x00 0x200>, 1278 <0x00 0x02728000 0x00 0x8000>; 1279 reg-names = "m_can", "message_ram"; 1280 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1281 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1282 clock-names = "hclk", "cclk"; 1283 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1285 interrupt-names = "int0", "int1"; 1286 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1287 status = "disabled"; 1288 }; 1289 1290 main_mcan3: can@2731000 { 1291 compatible = "bosch,m_can"; 1292 reg = <0x00 0x02731000 0x00 0x200>, 1293 <0x00 0x02738000 0x00 0x8000>; 1294 reg-names = "m_can", "message_ram"; 1295 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1296 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1297 clock-names = "hclk", "cclk"; 1298 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1300 interrupt-names = "int0", "int1"; 1301 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1302 status = "disabled"; 1303 }; 1304 1305 main_mcan4: can@2741000 { 1306 compatible = "bosch,m_can"; 1307 reg = <0x00 0x02741000 0x00 0x200>, 1308 <0x00 0x02748000 0x00 0x8000>; 1309 reg-names = "m_can", "message_ram"; 1310 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1311 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1312 clock-names = "hclk", "cclk"; 1313 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1315 interrupt-names = "int0", "int1"; 1316 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1317 status = "disabled"; 1318 }; 1319 1320 main_mcan5: can@2751000 { 1321 compatible = "bosch,m_can"; 1322 reg = <0x00 0x02751000 0x00 0x200>, 1323 <0x00 0x02758000 0x00 0x8000>; 1324 reg-names = "m_can", "message_ram"; 1325 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1326 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1327 clock-names = "hclk", "cclk"; 1328 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1330 interrupt-names = "int0", "int1"; 1331 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1332 status = "disabled"; 1333 }; 1334 1335 main_mcan6: can@2761000 { 1336 compatible = "bosch,m_can"; 1337 reg = <0x00 0x02761000 0x00 0x200>, 1338 <0x00 0x02768000 0x00 0x8000>; 1339 reg-names = "m_can", "message_ram"; 1340 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1341 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1342 clock-names = "hclk", "cclk"; 1343 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1345 interrupt-names = "int0", "int1"; 1346 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1347 status = "disabled"; 1348 }; 1349 1350 main_mcan7: can@2771000 { 1351 compatible = "bosch,m_can"; 1352 reg = <0x00 0x02771000 0x00 0x200>, 1353 <0x00 0x02778000 0x00 0x8000>; 1354 reg-names = "m_can", "message_ram"; 1355 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1356 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1357 clock-names = "hclk", "cclk"; 1358 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1360 interrupt-names = "int0", "int1"; 1361 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1362 status = "disabled"; 1363 }; 1364 1365 main_mcan8: can@2781000 { 1366 compatible = "bosch,m_can"; 1367 reg = <0x00 0x02781000 0x00 0x200>, 1368 <0x00 0x02788000 0x00 0x8000>; 1369 reg-names = "m_can", "message_ram"; 1370 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1371 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1372 clock-names = "hclk", "cclk"; 1373 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1375 interrupt-names = "int0", "int1"; 1376 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1377 status = "disabled"; 1378 }; 1379 1380 main_mcan9: can@2791000 { 1381 compatible = "bosch,m_can"; 1382 reg = <0x00 0x02791000 0x00 0x200>, 1383 <0x00 0x02798000 0x00 0x8000>; 1384 reg-names = "m_can", "message_ram"; 1385 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1386 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1387 clock-names = "hclk", "cclk"; 1388 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1390 interrupt-names = "int0", "int1"; 1391 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1392 status = "disabled"; 1393 }; 1394 1395 main_mcan10: can@27a1000 { 1396 compatible = "bosch,m_can"; 1397 reg = <0x00 0x027a1000 0x00 0x200>, 1398 <0x00 0x027a8000 0x00 0x8000>; 1399 reg-names = "m_can", "message_ram"; 1400 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1401 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1402 clock-names = "hclk", "cclk"; 1403 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1405 interrupt-names = "int0", "int1"; 1406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1407 status = "disabled"; 1408 }; 1409 1410 main_mcan11: can@27b1000 { 1411 compatible = "bosch,m_can"; 1412 reg = <0x00 0x027b1000 0x00 0x200>, 1413 <0x00 0x027b8000 0x00 0x8000>; 1414 reg-names = "m_can", "message_ram"; 1415 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1416 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1417 clock-names = "hclk", "cclk"; 1418 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1420 interrupt-names = "int0", "int1"; 1421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1422 status = "disabled"; 1423 }; 1424 1425 main_mcan12: can@27c1000 { 1426 compatible = "bosch,m_can"; 1427 reg = <0x00 0x027c1000 0x00 0x200>, 1428 <0x00 0x027c8000 0x00 0x8000>; 1429 reg-names = "m_can", "message_ram"; 1430 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1431 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1432 clock-names = "hclk", "cclk"; 1433 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1435 interrupt-names = "int0", "int1"; 1436 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1437 status = "disabled"; 1438 }; 1439 1440 main_mcan13: can@27d1000 { 1441 compatible = "bosch,m_can"; 1442 reg = <0x00 0x027d1000 0x00 0x200>, 1443 <0x00 0x027d8000 0x00 0x8000>; 1444 reg-names = "m_can", "message_ram"; 1445 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1446 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1447 clock-names = "hclk", "cclk"; 1448 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1450 interrupt-names = "int0", "int1"; 1451 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1452 status = "disabled"; 1453 }; 1454 1455 main_mcan14: can@2681000 { 1456 compatible = "bosch,m_can"; 1457 reg = <0x00 0x02681000 0x00 0x200>, 1458 <0x00 0x02688000 0x00 0x8000>; 1459 reg-names = "m_can", "message_ram"; 1460 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1461 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1462 clock-names = "hclk", "cclk"; 1463 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1465 interrupt-names = "int0", "int1"; 1466 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1467 status = "disabled"; 1468 }; 1469 1470 main_mcan15: can@2691000 { 1471 compatible = "bosch,m_can"; 1472 reg = <0x00 0x02691000 0x00 0x200>, 1473 <0x00 0x02698000 0x00 0x8000>; 1474 reg-names = "m_can", "message_ram"; 1475 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1476 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1477 clock-names = "hclk", "cclk"; 1478 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1480 interrupt-names = "int0", "int1"; 1481 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1482 status = "disabled"; 1483 }; 1484 1485 main_mcan16: can@26a1000 { 1486 compatible = "bosch,m_can"; 1487 reg = <0x00 0x026a1000 0x00 0x200>, 1488 <0x00 0x026a8000 0x00 0x8000>; 1489 reg-names = "m_can", "message_ram"; 1490 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1491 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1492 clock-names = "hclk", "cclk"; 1493 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1495 interrupt-names = "int0", "int1"; 1496 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1497 status = "disabled"; 1498 }; 1499 1500 main_mcan17: can@26b1000 { 1501 compatible = "bosch,m_can"; 1502 reg = <0x00 0x026b1000 0x00 0x200>, 1503 <0x00 0x026b8000 0x00 0x8000>; 1504 reg-names = "m_can", "message_ram"; 1505 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1506 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1507 clock-names = "hclk", "cclk"; 1508 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1510 interrupt-names = "int0", "int1"; 1511 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1512 status = "disabled"; 1513 }; 1514 1515 main_spi0: spi@2100000 { 1516 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1517 reg = <0x00 0x02100000 0x00 0x400>; 1518 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1522 clocks = <&k3_clks 376 1>; 1523 status = "disabled"; 1524 }; 1525 1526 main_spi1: spi@2110000 { 1527 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1528 reg = <0x00 0x02110000 0x00 0x400>; 1529 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1533 clocks = <&k3_clks 377 1>; 1534 status = "disabled"; 1535 }; 1536 1537 main_spi2: spi@2120000 { 1538 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1539 reg = <0x00 0x02120000 0x00 0x400>; 1540 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1544 clocks = <&k3_clks 378 1>; 1545 status = "disabled"; 1546 }; 1547 1548 main_spi3: spi@2130000 { 1549 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1550 reg = <0x00 0x02130000 0x00 0x400>; 1551 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1555 clocks = <&k3_clks 379 1>; 1556 status = "disabled"; 1557 }; 1558 1559 main_spi4: spi@2140000 { 1560 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1561 reg = <0x00 0x02140000 0x00 0x400>; 1562 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1566 clocks = <&k3_clks 380 1>; 1567 status = "disabled"; 1568 }; 1569 1570 main_spi5: spi@2150000 { 1571 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1572 reg = <0x00 0x02150000 0x00 0x400>; 1573 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1577 clocks = <&k3_clks 381 1>; 1578 status = "disabled"; 1579 }; 1580 1581 main_spi6: spi@2160000 { 1582 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1583 reg = <0x00 0x02160000 0x00 0x400>; 1584 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1588 clocks = <&k3_clks 382 1>; 1589 status = "disabled"; 1590 }; 1591 1592 main_spi7: spi@2170000 { 1593 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1594 reg = <0x00 0x02170000 0x00 0x400>; 1595 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1599 clocks = <&k3_clks 383 1>; 1600 status = "disabled"; 1601 }; 1602 1603 ufs_wrapper: ufs-wrapper@4e80000 { 1604 compatible = "ti,j721e-ufs"; 1605 reg = <0x00 0x4e80000 0x00 0x100>; 1606 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1607 clocks = <&k3_clks 387 3>; 1608 assigned-clocks = <&k3_clks 387 3>; 1609 assigned-clock-parents = <&k3_clks 387 6>; 1610 ranges; 1611 #address-cells = <2>; 1612 #size-cells = <2>; 1613 status = "disabled"; 1614 1615 ufs@4e84000 { 1616 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1617 reg = <0x00 0x4e84000 0x00 0x10000>; 1618 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1619 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1620 <19200000 19200000>; 1621 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1622 clock-names = "core_clk", "phy_clk", "ref_clk"; 1623 dma-coherent; 1624 }; 1625 }; 1626 1627 main_r5fss0: r5fss@5c00000 { 1628 compatible = "ti,j721s2-r5fss"; 1629 ti,cluster-mode = <1>; 1630 #address-cells = <1>; 1631 #size-cells = <1>; 1632 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1633 <0x5d00000 0x00 0x5d00000 0x20000>; 1634 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1635 1636 main_r5fss0_core0: r5f@5c00000 { 1637 compatible = "ti,j721s2-r5f"; 1638 reg = <0x5c00000 0x00010000>, 1639 <0x5c10000 0x00010000>; 1640 reg-names = "atcm", "btcm"; 1641 ti,sci = <&sms>; 1642 ti,sci-dev-id = <339>; 1643 ti,sci-proc-ids = <0x06 0xff>; 1644 resets = <&k3_reset 339 1>; 1645 firmware-name = "j784s4-main-r5f0_0-fw"; 1646 ti,atcm-enable = <1>; 1647 ti,btcm-enable = <1>; 1648 ti,loczrama = <1>; 1649 }; 1650 1651 main_r5fss0_core1: r5f@5d00000 { 1652 compatible = "ti,j721s2-r5f"; 1653 reg = <0x5d00000 0x00010000>, 1654 <0x5d10000 0x00010000>; 1655 reg-names = "atcm", "btcm"; 1656 ti,sci = <&sms>; 1657 ti,sci-dev-id = <340>; 1658 ti,sci-proc-ids = <0x07 0xff>; 1659 resets = <&k3_reset 340 1>; 1660 firmware-name = "j784s4-main-r5f0_1-fw"; 1661 ti,atcm-enable = <1>; 1662 ti,btcm-enable = <1>; 1663 ti,loczrama = <1>; 1664 }; 1665 }; 1666 1667 main_r5fss1: r5fss@5e00000 { 1668 compatible = "ti,j721s2-r5fss"; 1669 ti,cluster-mode = <1>; 1670 #address-cells = <1>; 1671 #size-cells = <1>; 1672 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1673 <0x5f00000 0x00 0x5f00000 0x20000>; 1674 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1675 1676 main_r5fss1_core0: r5f@5e00000 { 1677 compatible = "ti,j721s2-r5f"; 1678 reg = <0x5e00000 0x00010000>, 1679 <0x5e10000 0x00010000>; 1680 reg-names = "atcm", "btcm"; 1681 ti,sci = <&sms>; 1682 ti,sci-dev-id = <341>; 1683 ti,sci-proc-ids = <0x08 0xff>; 1684 resets = <&k3_reset 341 1>; 1685 firmware-name = "j784s4-main-r5f1_0-fw"; 1686 ti,atcm-enable = <1>; 1687 ti,btcm-enable = <1>; 1688 ti,loczrama = <1>; 1689 }; 1690 1691 main_r5fss1_core1: r5f@5f00000 { 1692 compatible = "ti,j721s2-r5f"; 1693 reg = <0x5f00000 0x00010000>, 1694 <0x5f10000 0x00010000>; 1695 reg-names = "atcm", "btcm"; 1696 ti,sci = <&sms>; 1697 ti,sci-dev-id = <342>; 1698 ti,sci-proc-ids = <0x09 0xff>; 1699 resets = <&k3_reset 342 1>; 1700 firmware-name = "j784s4-main-r5f1_1-fw"; 1701 ti,atcm-enable = <1>; 1702 ti,btcm-enable = <1>; 1703 ti,loczrama = <1>; 1704 }; 1705 }; 1706 1707 main_r5fss2: r5fss@5900000 { 1708 compatible = "ti,j721s2-r5fss"; 1709 ti,cluster-mode = <1>; 1710 #address-cells = <1>; 1711 #size-cells = <1>; 1712 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1713 <0x5a00000 0x00 0x5a00000 0x20000>; 1714 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1715 1716 main_r5fss2_core0: r5f@5900000 { 1717 compatible = "ti,j721s2-r5f"; 1718 reg = <0x5900000 0x00010000>, 1719 <0x5910000 0x00010000>; 1720 reg-names = "atcm", "btcm"; 1721 ti,sci = <&sms>; 1722 ti,sci-dev-id = <343>; 1723 ti,sci-proc-ids = <0x0a 0xff>; 1724 resets = <&k3_reset 343 1>; 1725 firmware-name = "j784s4-main-r5f2_0-fw"; 1726 ti,atcm-enable = <1>; 1727 ti,btcm-enable = <1>; 1728 ti,loczrama = <1>; 1729 }; 1730 1731 main_r5fss2_core1: r5f@5a00000 { 1732 compatible = "ti,j721s2-r5f"; 1733 reg = <0x5a00000 0x00010000>, 1734 <0x5a10000 0x00010000>; 1735 reg-names = "atcm", "btcm"; 1736 ti,sci = <&sms>; 1737 ti,sci-dev-id = <344>; 1738 ti,sci-proc-ids = <0x0b 0xff>; 1739 resets = <&k3_reset 344 1>; 1740 firmware-name = "j784s4-main-r5f2_1-fw"; 1741 ti,atcm-enable = <1>; 1742 ti,btcm-enable = <1>; 1743 ti,loczrama = <1>; 1744 }; 1745 }; 1746 1747 c71_0: dsp@64800000 { 1748 compatible = "ti,j721s2-c71-dsp"; 1749 reg = <0x00 0x64800000 0x00 0x00080000>, 1750 <0x00 0x64e00000 0x00 0x0000c000>; 1751 reg-names = "l2sram", "l1dram"; 1752 ti,sci = <&sms>; 1753 ti,sci-dev-id = <30>; 1754 ti,sci-proc-ids = <0x30 0xff>; 1755 resets = <&k3_reset 30 1>; 1756 firmware-name = "j784s4-c71_0-fw"; 1757 status = "disabled"; 1758 }; 1759 1760 c71_1: dsp@65800000 { 1761 compatible = "ti,j721s2-c71-dsp"; 1762 reg = <0x00 0x65800000 0x00 0x00080000>, 1763 <0x00 0x65e00000 0x00 0x0000c000>; 1764 reg-names = "l2sram", "l1dram"; 1765 ti,sci = <&sms>; 1766 ti,sci-dev-id = <33>; 1767 ti,sci-proc-ids = <0x31 0xff>; 1768 resets = <&k3_reset 33 1>; 1769 firmware-name = "j784s4-c71_1-fw"; 1770 status = "disabled"; 1771 }; 1772 1773 c71_2: dsp@66800000 { 1774 compatible = "ti,j721s2-c71-dsp"; 1775 reg = <0x00 0x66800000 0x00 0x00080000>, 1776 <0x00 0x66e00000 0x00 0x0000c000>; 1777 reg-names = "l2sram", "l1dram"; 1778 ti,sci = <&sms>; 1779 ti,sci-dev-id = <37>; 1780 ti,sci-proc-ids = <0x32 0xff>; 1781 resets = <&k3_reset 37 1>; 1782 firmware-name = "j784s4-c71_2-fw"; 1783 status = "disabled"; 1784 }; 1785 1786 c71_3: dsp@67800000 { 1787 compatible = "ti,j721s2-c71-dsp"; 1788 reg = <0x00 0x67800000 0x00 0x00080000>, 1789 <0x00 0x67e00000 0x00 0x0000c000>; 1790 reg-names = "l2sram", "l1dram"; 1791 ti,sci = <&sms>; 1792 ti,sci-dev-id = <40>; 1793 ti,sci-proc-ids = <0x33 0xff>; 1794 resets = <&k3_reset 40 1>; 1795 firmware-name = "j784s4-c71_3-fw"; 1796 status = "disabled"; 1797 }; 1798 1799 main_esm: esm@700000 { 1800 compatible = "ti,j721e-esm"; 1801 reg = <0x00 0x700000 0x00 0x1000>; 1802 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 1803 <695>; 1804 bootph-pre-ram; 1805 }; 1806 1807 watchdog0: watchdog@2200000 { 1808 compatible = "ti,j7-rti-wdt"; 1809 reg = <0x00 0x2200000 0x00 0x100>; 1810 clocks = <&k3_clks 348 1>; 1811 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 1812 assigned-clocks = <&k3_clks 348 0>; 1813 assigned-clock-parents = <&k3_clks 348 4>; 1814 }; 1815 1816 watchdog1: watchdog@2210000 { 1817 compatible = "ti,j7-rti-wdt"; 1818 reg = <0x00 0x2210000 0x00 0x100>; 1819 clocks = <&k3_clks 349 1>; 1820 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 1821 assigned-clocks = <&k3_clks 349 0>; 1822 assigned-clock-parents = <&k3_clks 349 4>; 1823 }; 1824 1825 watchdog2: watchdog@2220000 { 1826 compatible = "ti,j7-rti-wdt"; 1827 reg = <0x00 0x2220000 0x00 0x100>; 1828 clocks = <&k3_clks 350 1>; 1829 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 1830 assigned-clocks = <&k3_clks 350 0>; 1831 assigned-clock-parents = <&k3_clks 350 4>; 1832 }; 1833 1834 watchdog3: watchdog@2230000 { 1835 compatible = "ti,j7-rti-wdt"; 1836 reg = <0x00 0x2230000 0x00 0x100>; 1837 clocks = <&k3_clks 351 1>; 1838 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 1839 assigned-clocks = <&k3_clks 351 0>; 1840 assigned-clock-parents = <&k3_clks 351 4>; 1841 }; 1842 1843 watchdog4: watchdog@2240000 { 1844 compatible = "ti,j7-rti-wdt"; 1845 reg = <0x00 0x2240000 0x00 0x100>; 1846 clocks = <&k3_clks 352 1>; 1847 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 1848 assigned-clocks = <&k3_clks 352 0>; 1849 assigned-clock-parents = <&k3_clks 352 4>; 1850 }; 1851 1852 watchdog5: watchdog@2250000 { 1853 compatible = "ti,j7-rti-wdt"; 1854 reg = <0x00 0x2250000 0x00 0x100>; 1855 clocks = <&k3_clks 353 1>; 1856 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 1857 assigned-clocks = <&k3_clks 353 0>; 1858 assigned-clock-parents = <&k3_clks 353 4>; 1859 }; 1860 1861 watchdog6: watchdog@2260000 { 1862 compatible = "ti,j7-rti-wdt"; 1863 reg = <0x00 0x2260000 0x00 0x100>; 1864 clocks = <&k3_clks 354 1>; 1865 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 1866 assigned-clocks = <&k3_clks 354 0>; 1867 assigned-clock-parents = <&k3_clks 354 4>; 1868 }; 1869 1870 watchdog7: watchdog@2270000 { 1871 compatible = "ti,j7-rti-wdt"; 1872 reg = <0x00 0x2270000 0x00 0x100>; 1873 clocks = <&k3_clks 355 1>; 1874 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 1875 assigned-clocks = <&k3_clks 355 0>; 1876 assigned-clock-parents = <&k3_clks 355 4>; 1877 }; 1878 1879 /* 1880 * The following RTI instances are coupled with MCU R5Fs, c7x and 1881 * GPU so keeping them reserved as these will be used by their 1882 * respective firmware 1883 */ 1884 watchdog8: watchdog@22f0000 { 1885 compatible = "ti,j7-rti-wdt"; 1886 reg = <0x00 0x22f0000 0x00 0x100>; 1887 clocks = <&k3_clks 360 1>; 1888 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1889 assigned-clocks = <&k3_clks 360 0>; 1890 assigned-clock-parents = <&k3_clks 360 4>; 1891 /* reserved for GPU */ 1892 status = "reserved"; 1893 }; 1894 1895 watchdog9: watchdog@2300000 { 1896 compatible = "ti,j7-rti-wdt"; 1897 reg = <0x00 0x2300000 0x00 0x100>; 1898 clocks = <&k3_clks 356 1>; 1899 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 1900 assigned-clocks = <&k3_clks 356 0>; 1901 assigned-clock-parents = <&k3_clks 356 4>; 1902 /* reserved for C7X_0 DSP */ 1903 status = "reserved"; 1904 }; 1905 1906 watchdog10: watchdog@2310000 { 1907 compatible = "ti,j7-rti-wdt"; 1908 reg = <0x00 0x2310000 0x00 0x100>; 1909 clocks = <&k3_clks 357 1>; 1910 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 1911 assigned-clocks = <&k3_clks 357 0>; 1912 assigned-clock-parents = <&k3_clks 357 4>; 1913 /* reserved for C7X_1 DSP */ 1914 status = "reserved"; 1915 }; 1916 1917 watchdog11: watchdog@2320000 { 1918 compatible = "ti,j7-rti-wdt"; 1919 reg = <0x00 0x2320000 0x00 0x100>; 1920 clocks = <&k3_clks 358 1>; 1921 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 1922 assigned-clocks = <&k3_clks 358 0>; 1923 assigned-clock-parents = <&k3_clks 358 4>; 1924 /* reserved for C7X_2 DSP */ 1925 status = "reserved"; 1926 }; 1927 1928 watchdog12: watchdog@2330000 { 1929 compatible = "ti,j7-rti-wdt"; 1930 reg = <0x00 0x2330000 0x00 0x100>; 1931 clocks = <&k3_clks 359 1>; 1932 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 1933 assigned-clocks = <&k3_clks 359 0>; 1934 assigned-clock-parents = <&k3_clks 359 4>; 1935 /* reserved for C7X_3 DSP */ 1936 status = "reserved"; 1937 }; 1938 1939 watchdog13: watchdog@23c0000 { 1940 compatible = "ti,j7-rti-wdt"; 1941 reg = <0x00 0x23c0000 0x00 0x100>; 1942 clocks = <&k3_clks 361 1>; 1943 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 1944 assigned-clocks = <&k3_clks 361 0>; 1945 assigned-clock-parents = <&k3_clks 361 4>; 1946 /* reserved for MAIN_R5F0_0 */ 1947 status = "reserved"; 1948 }; 1949 1950 watchdog14: watchdog@23d0000 { 1951 compatible = "ti,j7-rti-wdt"; 1952 reg = <0x00 0x23d0000 0x00 0x100>; 1953 clocks = <&k3_clks 362 1>; 1954 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 1955 assigned-clocks = <&k3_clks 362 0>; 1956 assigned-clock-parents = <&k3_clks 362 4>; 1957 /* reserved for MAIN_R5F0_1 */ 1958 status = "reserved"; 1959 }; 1960 1961 watchdog15: watchdog@23e0000 { 1962 compatible = "ti,j7-rti-wdt"; 1963 reg = <0x00 0x23e0000 0x00 0x100>; 1964 clocks = <&k3_clks 363 1>; 1965 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 1966 assigned-clocks = <&k3_clks 363 0>; 1967 assigned-clock-parents = <&k3_clks 363 4>; 1968 /* reserved for MAIN_R5F1_0 */ 1969 status = "reserved"; 1970 }; 1971 1972 watchdog16: watchdog@23f0000 { 1973 compatible = "ti,j7-rti-wdt"; 1974 reg = <0x00 0x23f0000 0x00 0x100>; 1975 clocks = <&k3_clks 364 1>; 1976 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 1977 assigned-clocks = <&k3_clks 364 0>; 1978 assigned-clock-parents = <&k3_clks 364 4>; 1979 /* reserved for MAIN_R5F1_1 */ 1980 status = "reserved"; 1981 }; 1982 1983 watchdog17: watchdog@2540000 { 1984 compatible = "ti,j7-rti-wdt"; 1985 reg = <0x00 0x2540000 0x00 0x100>; 1986 clocks = <&k3_clks 365 1>; 1987 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1988 assigned-clocks = <&k3_clks 365 0>; 1989 assigned-clock-parents = <&k3_clks 366 4>; 1990 /* reserved for MAIN_R5F2_0 */ 1991 status = "reserved"; 1992 }; 1993 1994 watchdog18: watchdog@2550000 { 1995 compatible = "ti,j7-rti-wdt"; 1996 reg = <0x00 0x2550000 0x00 0x100>; 1997 clocks = <&k3_clks 366 1>; 1998 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 1999 assigned-clocks = <&k3_clks 366 0>; 2000 assigned-clock-parents = <&k3_clks 366 4>; 2001 /* reserved for MAIN_R5F2_1 */ 2002 status = "reserved"; 2003 }; 2004 2005 mhdp: bridge@a000000 { 2006 compatible = "ti,j721e-mhdp8546"; 2007 reg = <0x0 0xa000000 0x0 0x30a00>, 2008 <0x0 0x4f40000 0x0 0x20>; 2009 reg-names = "mhdptx", "j721e-intg"; 2010 clocks = <&k3_clks 217 11>; 2011 interrupt-parent = <&gic500>; 2012 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2013 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2014 status = "disabled"; 2015 2016 dp0_ports: ports { 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 /* Remote-endpoints are on the boards so 2020 * ports are defined in the platform dt file. 2021 */ 2022 }; 2023 }; 2024 2025 dss: dss@4a00000 { 2026 compatible = "ti,j721e-dss"; 2027 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2028 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2029 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2030 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2031 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2032 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2033 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2034 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2035 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2036 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2037 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2038 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2039 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2040 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2041 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2042 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2043 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2044 reg-names = "common_m", "common_s0", 2045 "common_s1", "common_s2", 2046 "vidl1", "vidl2","vid1","vid2", 2047 "ovr1", "ovr2", "ovr3", "ovr4", 2048 "vp1", "vp2", "vp3", "vp4", 2049 "wb"; 2050 clocks = <&k3_clks 218 0>, 2051 <&k3_clks 218 2>, 2052 <&k3_clks 218 5>, 2053 <&k3_clks 218 14>, 2054 <&k3_clks 218 18>; 2055 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2056 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2057 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2061 interrupt-names = "common_m", 2062 "common_s0", 2063 "common_s1", 2064 "common_s2"; 2065 status = "disabled"; 2066 2067 dss_ports: ports { 2068 /* Ports that DSS drives are platform specific 2069 * so they are defined in platform dt file. 2070 */ 2071 }; 2072 }; 2073}; 2074