1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the J722S EVM 4 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Schematics: https://www.ti.com/lit/zip/sprr495 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include "k3-j722s.dtsi" 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,j722s-evm", "ti,j722s"; 18 model = "Texas Instruments J722S EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart5; 24 mmc0 = &sdhci0; 25 mmc1 = &sdhci1; 26 }; 27 28 chosen { 29 stdout-path = &main_uart0; 30 }; 31 32 memory@80000000 { 33 /* 8G RAM */ 34 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 35 <0x00000008 0x80000000 0x00000001 0x80000000>; 36 device_type = "memory"; 37 bootph-pre-ram; 38 }; 39 40 reserved_memory: reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 secure_tfa_ddr: tfa@9e780000 { 46 reg = <0x00 0x9e780000 0x00 0x80000>; 47 no-map; 48 }; 49 50 secure_ddr: optee@9e800000 { 51 reg = <0x00 0x9e800000 0x00 0x01800000>; 52 no-map; 53 }; 54 55 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0000000 0x00 0x100000>; 58 no-map; 59 }; 60 61 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa0100000 0x00 0xf00000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1000000 0x00 0x100000>; 70 no-map; 71 }; 72 73 mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa1100000 0x00 0xf00000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2000000 0x00 0x100000>; 82 no-map; 83 }; 84 85 main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa2100000 0x00 0xf00000>; 88 no-map; 89 }; 90 91 c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3000000 0x00 0x100000>; 94 no-map; 95 }; 96 97 c7x_0_memory_region: c7x-memory@a3100000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa3100000 0x00 0xf00000>; 100 no-map; 101 }; 102 103 c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4000000 0x00 0x100000>; 106 no-map; 107 }; 108 109 c7x_1_memory_region: c7x-memory@a4100000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa4100000 0x00 0xf00000>; 112 no-map; 113 }; 114 115 rtos_ipc_memory_region: ipc-memories@a5000000 { 116 reg = <0x00 0xa5000000 0x00 0x1c00000>; 117 alignment = <0x1000>; 118 no-map; 119 }; 120 }; 121 122 vmain_pd: regulator-0 { 123 /* TPS65988 PD CONTROLLER OUTPUT */ 124 compatible = "regulator-fixed"; 125 regulator-name = "vmain_pd"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 regulator-always-on; 129 regulator-boot-on; 130 bootph-all; 131 }; 132 133 vsys_5v0: regulator-vsys5v0 { 134 /* Output of LM5140 */ 135 compatible = "regulator-fixed"; 136 regulator-name = "vsys_5v0"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 vin-supply = <&vmain_pd>; 140 regulator-always-on; 141 regulator-boot-on; 142 }; 143 144 vsys_3v3: regulator-vsys3v3 { 145 /* output of LM5141-Q1 */ 146 compatible = "regulator-fixed"; 147 regulator-name = "vsys_3v3"; 148 regulator-min-microvolt = <3300000>; 149 regulator-max-microvolt = <3300000>; 150 vin-supply = <&vmain_pd>; 151 regulator-always-on; 152 regulator-boot-on; 153 }; 154 155 vdd_mmc1: regulator-mmc1 { 156 /* TPS22918DBVR */ 157 compatible = "regulator-fixed"; 158 regulator-name = "vdd_mmc1"; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 regulator-boot-on; 162 enable-active-high; 163 gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; 164 bootph-all; 165 }; 166 167 vsys_3v3_exp: regulator-TPS22990 { 168 /* output of TPS22990 */ 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_3v3_exp"; 171 regulator-min-microvolt = <3300000>; 172 regulator-max-microvolt = <3300000>; 173 vin-supply = <&vsys_3v3>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vdd_sd_dv: regulator-TLV71033 { 179 compatible = "regulator-gpio"; 180 regulator-name = "tlv71033"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&vdd_sd_dv_pins_default>; 183 regulator-min-microvolt = <1800000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 vin-supply = <&vsys_5v0>; 187 gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; 188 states = <1800000 0x0>, 189 <3300000 0x1>; 190 }; 191 192 vsys_io_3v3: regulator-vsys-io-3v3 { 193 compatible = "regulator-fixed"; 194 regulator-name = "vsys_io_3v3"; 195 regulator-min-microvolt = <3300000>; 196 regulator-max-microvolt = <3300000>; 197 regulator-always-on; 198 regulator-boot-on; 199 }; 200 201 vsys_io_1v8: regulator-vsys-io-1v8 { 202 compatible = "regulator-fixed"; 203 regulator-name = "vsys_io_1v8"; 204 regulator-min-microvolt = <1800000>; 205 regulator-max-microvolt = <1800000>; 206 regulator-always-on; 207 regulator-boot-on; 208 }; 209 210 vsys_io_1v2: regulator-vsys-io-1v2 { 211 compatible = "regulator-fixed"; 212 regulator-name = "vsys_io_1v2"; 213 regulator-min-microvolt = <1200000>; 214 regulator-max-microvolt = <1200000>; 215 regulator-always-on; 216 regulator-boot-on; 217 }; 218 219 codec_audio: sound { 220 compatible = "simple-audio-card"; 221 simple-audio-card,name = "J722S-EVM"; 222 simple-audio-card,widgets = 223 "Headphone", "Headphone Jack", 224 "Line", "Line In", 225 "Microphone", "Microphone Jack"; 226 simple-audio-card,routing = 227 "Headphone Jack", "HPLOUT", 228 "Headphone Jack", "HPROUT", 229 "LINE1L", "Line In", 230 "LINE1R", "Line In", 231 "MIC3R", "Microphone Jack", 232 "Microphone Jack", "Mic Bias"; 233 simple-audio-card,format = "dsp_b"; 234 simple-audio-card,bitclock-master = <&sound_master>; 235 simple-audio-card,frame-master = <&sound_master>; 236 simple-audio-card,bitclock-inversion; 237 238 simple-audio-card,cpu { 239 sound-dai = <&mcasp1>; 240 }; 241 242 sound_master: simple-audio-card,codec { 243 sound-dai = <&tlv320aic3106>; 244 clocks = <&audio_refclk1>; 245 }; 246 }; 247 248 transceiver0: can-phy0 { 249 compatible = "ti,tcan1042"; 250 #phy-cells = <0>; 251 max-bitrate = <5000000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 254 standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>; 255 }; 256 257 transceiver1: can-phy1 { 258 compatible = "ti,tcan1042"; 259 #phy-cells = <0>; 260 max-bitrate = <5000000>; 261 }; 262 263 transceiver2: can-phy2 { 264 compatible = "ti,tcan1042"; 265 #phy-cells = <0>; 266 max-bitrate = <5000000>; 267 standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>; 268 }; 269 270 csi01_mux: mux-controller-0 { 271 compatible = "gpio-mux"; 272 #mux-state-cells = <1>; 273 mux-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 274 idle-state = <0>; 275 }; 276 277 csi23_mux: mux-controller-1 { 278 compatible = "gpio-mux"; 279 #mux-state-cells = <1>; 280 mux-gpios = <&exp1 7 GPIO_ACTIVE_HIGH>; 281 idle-state = <0>; 282 }; 283}; 284 285&cpsw_mac_syscon { 286 bootph-all; 287}; 288 289&phy_gmii_sel { 290 bootph-all; 291}; 292 293&main_pmx0 { 294 295 main_mcan0_pins_default: main-mcan0-default-pins { 296 pinctrl-single,pins = < 297 J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */ 298 J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */ 299 >; 300 }; 301 302 main_i2c0_pins_default: main-i2c0-default-pins { 303 pinctrl-single,pins = < 304 J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ 305 J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ 306 >; 307 bootph-all; 308 }; 309 310 main_i2c2_pins_default: main-i2c2-default-pins { 311 pinctrl-single,pins = < 312 J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ 313 J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ 314 >; 315 }; 316 317 main_uart0_pins_default: main-uart0-default-pins { 318 pinctrl-single,pins = < 319 J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 320 J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 321 >; 322 bootph-all; 323 }; 324 325 main_uart5_pins_default: main-uart5-default-pins { 326 pinctrl-single,pins = < 327 J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */ 328 J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */ 329 >; 330 }; 331 332 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 333 pinctrl-single,pins = < 334 J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ 335 >; 336 bootph-all; 337 }; 338 339 main_mmc1_pins_default: main-mmc1-default-pins { 340 pinctrl-single,pins = < 341 J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ 342 J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ 343 J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ 344 J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ 345 J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ 346 J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ 347 J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ 348 >; 349 bootph-all; 350 }; 351 352 mdio_pins_default: mdio-default-pins { 353 pinctrl-single,pins = < 354 J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ 355 J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ 356 >; 357 bootph-all; 358 }; 359 360 ospi0_pins_default: ospi0-default-pins { 361 pinctrl-single,pins = < 362 J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ 363 J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ 364 J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ 365 J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ 366 J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ 367 J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ 368 J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ 369 J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ 370 J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ 371 J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ 372 J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ 373 >; 374 bootph-all; 375 }; 376 377 rgmii1_pins_default: rgmii1-default-pins { 378 pinctrl-single,pins = < 379 J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ 380 J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ 381 J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ 382 J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ 383 J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ 384 J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ 385 J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ 386 J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ 387 J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ 388 J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ 389 J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ 390 J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ 391 >; 392 bootph-all; 393 }; 394 395 main_usb1_pins_default: main-usb1-default-pins { 396 pinctrl-single,pins = < 397 J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ 398 >; 399 }; 400 401 main_mcasp1_pins_default: main-mcasp1-default-pins { 402 pinctrl-single,pins = < 403 J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */ 404 J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */ 405 J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */ 406 J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */ 407 >; 408 }; 409 410 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 411 pinctrl-single,pins = < 412 J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ 413 >; 414 }; 415 416 pmic_irq_pins_default: pmic-irq-default-pins { 417 pinctrl-single,pins = < 418 J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */ 419 >; 420 }; 421 422}; 423 424&cpsw3g { 425 status = "okay"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&rgmii1_pins_default>; 428}; 429 430&cpsw3g_mdio { 431 status = "okay"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&mdio_pins_default>; 434 435 cpsw3g_phy0: ethernet-phy@0 { 436 reg = <0>; 437 bootph-all; 438 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 439 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 440 ti,min-output-impedance; 441 }; 442}; 443 444&cpsw_port1 { 445 phy-mode = "rgmii-rxid"; 446 phy-handle = <&cpsw3g_phy0>; 447 status = "okay"; 448 bootph-all; 449}; 450 451&main_gpio1 { 452 status = "okay"; 453}; 454 455&main_uart0 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&main_uart0_pins_default>; 458 status = "okay"; 459 bootph-all; 460}; 461 462&main_uart5 { 463 /* MAIN UART 5 is used by System firmware */ 464 pinctrl-names = "default"; 465 pinctrl-0 = <&main_uart5_pins_default>; 466 status = "reserved"; 467}; 468 469&mcu_pmx0 { 470 471 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 472 pinctrl-single,pins = < 473 J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ 474 J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ 475 >; 476 }; 477 478 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 479 pinctrl-single,pins = < 480 J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ 481 J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ 482 >; 483 }; 484 485 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 486 pinctrl-single,pins = < 487 J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ 488 J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ 489 >; 490 }; 491 492 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 493 pinctrl-single,pins = < 494 J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */ 495 >; 496 }; 497 498 wkup_uart0_pins_default: wkup-uart0-default-pins { 499 pinctrl-single,pins = < 500 J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 501 J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 502 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 503 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 504 >; 505 bootph-all; 506 }; 507 508 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 509 pinctrl-single,pins = < 510 J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ 511 J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ 512 >; 513 bootph-all; 514 }; 515}; 516 517&wkup_uart0 { 518 /* WKUP UART0 is used by Device Manager firmware */ 519 pinctrl-names = "default"; 520 pinctrl-0 = <&wkup_uart0_pins_default>; 521 status = "reserved"; 522 bootph-all; 523}; 524 525&wkup_i2c0 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&wkup_i2c0_pins_default>; 528 clock-frequency = <400000>; 529 status = "okay"; 530 bootph-all; 531 532 tps65224: pmic@48 { 533 compatible = "ti,tps65224-q1"; 534 reg = <0x48>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pmic_irq_pins_default>; 537 interrupt-parent = <&main_gpio0>; 538 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 539 ti,primary-pmic; 540 541 gpio-controller; 542 #gpio-cells = <2>; 543 544 buck12-supply = <&vsys_io_3v3>; 545 buck3-supply = <&vsys_io_3v3>; 546 buck4-supply = <&vsys_io_3v3>; 547 548 ldo1-supply = <&vsys_io_3v3>; 549 ldo2-supply = <&vsys_io_3v3>; 550 ldo3-supply = <&vsys_io_3v3>; 551 552 regulators { 553 554 buck1: buck1 { 555 regulator-name = "vcc1v8_io_buck1"; 556 regulator-min-microvolt = <1800000>; 557 regulator-max-microvolt = <1800000>; 558 regulator-boot-on; 559 regulator-always-on; 560 bootph-all; 561 }; 562 563 buck2: buck2 { 564 regulator-name = "vcc1v1_ddr_buck2"; 565 regulator-min-microvolt = <1100000>; 566 regulator-max-microvolt = <1100000>; 567 regulator-boot-on; 568 regulator-always-on; 569 }; 570 571 buck3: buck3 { 572 regulator-name = "vcc0v85_ram_buck3"; 573 regulator-min-microvolt = <850000>; 574 regulator-max-microvolt = <850000>; 575 regulator-boot-on; 576 regulator-always-on; 577 }; 578 579 buck4: buck4 { 580 regulator-name = "vcc0v75_ioret_buck4"; 581 regulator-min-microvolt = <750000>; 582 regulator-max-microvolt = <750000>; 583 regulator-boot-on; 584 regulator-always-on; 585 }; 586 587 ldo1: ldo1 { 588 regulator-name = "vdda1v8_pll_ldo1"; 589 regulator-min-microvolt = <1800000>; 590 regulator-max-microvolt = <1800000>; 591 regulator-boot-on; 592 regulator-always-on; 593 }; 594 595 ldo2: ldo2 { 596 regulator-name = "dvdd3v3_ldo2"; 597 regulator-min-microvolt = <3300000>; 598 regulator-max-microvolt = <3300000>; 599 regulator-boot-on; 600 regulator-always-on; 601 }; 602 603 ldo3: ldo3 { 604 regulator-name = "vdd1v85_phy_ldo3"; 605 regulator-min-microvolt = <1800000>; 606 regulator-max-microvolt = <1800000>; 607 regulator-boot-on; 608 regulator-always-on; 609 }; 610 }; 611 }; 612}; 613 614&k3_clks { 615 /* Configure AUDIO_EXT_REFCLK1 pin as output */ 616 pinctrl-names = "default"; 617 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 618}; 619 620&main_i2c0 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&main_i2c0_pins_default>; 623 clock-frequency = <400000>; 624 status = "okay"; 625 bootph-all; 626 627 exp1: gpio@23 { 628 compatible = "ti,tca6424"; 629 reg = <0x23>; 630 gpio-controller; 631 #gpio-cells = <2>; 632 gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", 633 "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", 634 "CSI_VIO_SEL", "USB2.0_MUX_SEL", 635 "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", 636 "LMK1_OE1", "LMK1_OE0", 637 "LMK2_OE0", "LMK2_OE1", 638 "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", 639 "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", 640 "USER_LED2", "MCAN0_STB", 641 "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", 642 "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", 643 "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; 644 645 p05-hog { 646 /* P05 - USB2.0_MUX_SEL */ 647 gpio-hog; 648 gpios = <5 GPIO_ACTIVE_LOW>; 649 output-low; 650 }; 651 652 p01_hog: p01-hog { 653 /* P01 - TRC_MUX_SEL */ 654 gpio-hog; 655 gpios = <0 GPIO_ACTIVE_HIGH>; 656 output-low; 657 line-name = "TRC_MUX_SEL"; 658 }; 659 660 p02_hog: p02-hog { 661 /* P02 - MCASP1_FET_SEL */ 662 gpio-hog; 663 gpios = <2 GPIO_ACTIVE_HIGH>; 664 output-high; 665 line-name = "MCASP1_FET_SEL"; 666 }; 667 668 p13_hog: p13-hog { 669 /* P13 - GPIO_AUD_RSTn */ 670 gpio-hog; 671 gpios = <13 GPIO_ACTIVE_HIGH>; 672 output-high; 673 line-name = "GPIO_AUD_RSTn"; 674 }; 675 }; 676 677 tlv320aic3106: audio-codec@1b { 678 #sound-dai-cells = <0>; 679 compatible = "ti,tlv320aic3106"; 680 reg = <0x1b>; 681 ai3x-micbias-vg = <1>; /* 2.0V */ 682 AVDD-supply = <&vsys_io_3v3>; 683 IOVDD-supply = <&vsys_io_3v3>; 684 DRVDD-supply = <&vsys_io_3v3>; 685 DVDD-supply = <&vsys_io_1v8>; 686 }; 687}; 688 689&main_i2c2 { 690 status = "okay"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&main_i2c2_pins_default>; 693 clock-frequency = <400000>; 694 695 pca9543_0: i2c-mux@70 { 696 compatible = "nxp,pca9543"; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 reg = <0x70>; 700 }; 701 702 pca9543_1: i2c-mux@71 { 703 compatible = "nxp,pca9543"; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 reg = <0x71>; 707 }; 708}; 709 710&ospi0 { 711 pinctrl-names = "default"; 712 pinctrl-0 = <&ospi0_pins_default>; 713 status = "okay"; 714 715 flash@0 { 716 compatible = "jedec,spi-nor"; 717 reg = <0x0>; 718 spi-tx-bus-width = <8>; 719 spi-rx-bus-width = <8>; 720 spi-max-frequency = <25000000>; 721 cdns,tshsl-ns = <60>; 722 cdns,tsd2d-ns = <60>; 723 cdns,tchsh-ns = <60>; 724 cdns,tslch-ns = <60>; 725 cdns,read-delay = <4>; 726 bootph-all; 727 728 partitions { 729 compatible = "fixed-partitions"; 730 #address-cells = <1>; 731 #size-cells = <1>; 732 733 partition@0 { 734 label = "ospi.tiboot3"; 735 reg = <0x00 0x80000>; 736 }; 737 738 partition@80000 { 739 label = "ospi.tispl"; 740 reg = <0x80000 0x200000>; 741 }; 742 743 partition@280000 { 744 label = "ospi.u-boot"; 745 reg = <0x280000 0x400000>; 746 }; 747 748 partition@680000 { 749 label = "ospi.env"; 750 reg = <0x680000 0x40000>; 751 }; 752 753 partition@6c0000 { 754 label = "ospi.env.backup"; 755 reg = <0x6c0000 0x40000>; 756 }; 757 758 partition@800000 { 759 label = "ospi.rootfs"; 760 reg = <0x800000 0x37c0000>; 761 }; 762 763 partition@3fc0000 { 764 label = "ospi.phypattern"; 765 reg = <0x3fc0000 0x40000>; 766 }; 767 }; 768 }; 769 770}; 771 772&sdhci0 { 773 disable-wp; 774 bootph-all; 775 ti,driver-strength-ohm = <50>; 776 status = "okay"; 777}; 778 779&sdhci1 { 780 /* SD/MMC */ 781 vmmc-supply = <&vdd_mmc1>; 782 vqmmc-supply = <&vdd_sd_dv>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&main_mmc1_pins_default>; 785 ti,driver-strength-ohm = <50>; 786 disable-wp; 787 status = "okay"; 788 bootph-all; 789}; 790 791&mailbox0_cluster0 { 792 status = "okay"; 793 794 mbox_wkup_r5_0: mbox-wkup-r5-0 { 795 ti,mbox-rx = <0 0 0>; 796 ti,mbox-tx = <1 0 0>; 797 }; 798}; 799 800&mailbox0_cluster1 { 801 status = "okay"; 802 803 mbox_mcu_r5_0: mbox-mcu-r5-0 { 804 ti,mbox-rx = <0 0 0>; 805 ti,mbox-tx = <1 0 0>; 806 }; 807}; 808 809&mailbox0_cluster2 { 810 status = "okay"; 811 812 mbox_c7x_0: mbox-c7x-0 { 813 ti,mbox-rx = <0 0 0>; 814 ti,mbox-tx = <1 0 0>; 815 }; 816}; 817 818&mailbox0_cluster3 { 819 status = "okay"; 820 821 mbox_main_r5_0: mbox-main-r5-0 { 822 ti,mbox-rx = <0 0 0>; 823 ti,mbox-tx = <1 0 0>; 824 }; 825 826 mbox_c7x_1: mbox-c7x-1 { 827 ti,mbox-rx = <2 0 0>; 828 ti,mbox-tx = <3 0 0>; 829 }; 830}; 831 832/* Timers are used by Remoteproc firmware */ 833&main_timer0 { 834 status = "reserved"; 835}; 836 837&main_timer1 { 838 status = "reserved"; 839}; 840 841&main_timer2 { 842 status = "reserved"; 843}; 844 845&wkup_r5fss0 { 846 status = "okay"; 847}; 848 849&wkup_r5fss0_core0 { 850 mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; 851 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 852 <&wkup_r5fss0_core0_memory_region>; 853}; 854 855&mcu_r5fss0 { 856 status = "okay"; 857}; 858 859&mcu_r5fss0_core0 { 860 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 861 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 862 <&mcu_r5fss0_core0_memory_region>; 863}; 864 865&main_r5fss0 { 866 status = "okay"; 867}; 868 869&main_r5fss0_core0 { 870 mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; 871 memory-region = <&main_r5fss0_core0_dma_memory_region>, 872 <&main_r5fss0_core0_memory_region>; 873}; 874 875&c7x_0 { 876 mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; 877 memory-region = <&c7x_0_dma_memory_region>, 878 <&c7x_0_memory_region>; 879 status = "okay"; 880}; 881 882&c7x_1 { 883 mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; 884 memory-region = <&c7x_1_dma_memory_region>, 885 <&c7x_1_memory_region>; 886 status = "okay"; 887}; 888 889&serdes_ln_ctrl { 890 idle-states = <J722S_SERDES0_LANE0_USB>, 891 <J722S_SERDES1_LANE0_PCIE0_LANE0>; 892}; 893 894&serdes_wiz0 { 895 status = "okay"; 896}; 897 898&serdes0 { 899 serdes0_usb_link: phy@0 { 900 reg = <0>; 901 cdns,num-lanes = <1>; 902 #phy-cells = <0>; 903 cdns,phy-type = <PHY_TYPE_USB3>; 904 resets = <&serdes_wiz0 1>; 905 }; 906}; 907 908&serdes_wiz1 { 909 status = "okay"; 910}; 911 912&serdes1 { 913 serdes1_pcie_link: phy@0 { 914 reg = <0>; 915 cdns,num-lanes = <1>; 916 #phy-cells = <0>; 917 cdns,phy-type = <PHY_TYPE_PCIE>; 918 resets = <&serdes_wiz1 1>; 919 }; 920}; 921 922&pcie0_rc { 923 reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; 924 phys = <&serdes1_pcie_link>; 925 phy-names = "pcie-phy"; 926 status = "okay"; 927}; 928 929&usbss0 { 930 ti,vbus-divider; 931 status = "okay"; 932}; 933 934&usb0 { 935 dr_mode = "otg"; 936 usb-role-switch; 937}; 938 939&usbss1 { 940 pinctrl-names = "default"; 941 pinctrl-0 = <&main_usb1_pins_default>; 942 ti,vbus-divider; 943 status = "okay"; 944}; 945 946&usb1 { 947 dr_mode = "host"; 948 maximum-speed = "super-speed"; 949 phys = <&serdes0_usb_link>; 950 phy-names = "cdns3,usb3-phy"; 951}; 952 953&mcasp1 { 954 status = "okay"; 955 #sound-dai-cells = <0>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&main_mcasp1_pins_default>; 958 op-mode = <0>; /* MCASP_IIS_MODE */ 959 tdm-slots = <2>; 960 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 961 1 0 2 0 962 0 0 0 0 963 0 0 0 0 964 0 0 0 0 965 >; 966}; 967 968&mcu_mcan0 { 969 pinctrl-names = "default"; 970 pinctrl-0 = <&mcu_mcan0_pins_default>; 971 phys = <&transceiver0>; 972 status = "okay"; 973}; 974 975&mcu_mcan1 { 976 pinctrl-names = "default"; 977 pinctrl-0 = <&mcu_mcan1_pins_default>; 978 phys = <&transceiver1>; 979 status = "okay"; 980}; 981 982&main_mcan0 { 983 pinctrl-names = "default"; 984 pinctrl-0 = <&main_mcan0_pins_default>; 985 phys = <&transceiver2>; 986 status = "okay"; 987}; 988 989&mcu_gpio0 { 990 status = "okay"; 991}; 992 993&mcu_i2c0 { 994 pinctrl-names = "default"; 995 pinctrl-0 = <&mcu_i2c0_pins_default>; 996 clock-frequency = <400000>; 997 status = "okay"; 998}; 999