1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SoM: https://www.ti.com/lit/zip/sprr439 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9 10#include "k3-j721s2.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 memory@80000000 { 15 device_type = "memory"; 16 /* 16 GB RAM */ 17 reg = <0x00 0x80000000 0x00 0x80000000>, 18 <0x08 0x80000000 0x03 0x80000000>; 19 }; 20 21 /* Reserving memory regions still pending */ 22 reserved_memory: reserved-memory { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 secure_ddr: optee@9e800000 { 28 reg = <0x00 0x9e800000 0x00 0x01800000>; 29 alignment = <0x1000>; 30 no-map; 31 }; 32 }; 33 34 transceiver0: can-phy0 { 35 /* standby pin has been grounded by default */ 36 compatible = "ti,tcan1042"; 37 #phy-cells = <0>; 38 max-bitrate = <5000000>; 39 }; 40}; 41 42&wkup_pmx0 { 43 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 44 pinctrl-single,pins = < 45 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 46 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 47 J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ 48 J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ 49 J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ 50 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 51 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 52 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 53 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 54 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 55 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 56 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 57 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 58 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 59 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ 60 >; 61 }; 62}; 63 64&wkup_pmx2 { 65 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 66 pinctrl-single,pins = < 67 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ 68 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ 69 >; 70 }; 71}; 72 73&main_pmx0 { 74 main_i2c0_pins_default: main-i2c0-default-pins { 75 pinctrl-single,pins = < 76 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ 77 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ 78 >; 79 }; 80 81 main_mcan16_pins_default: main-mcan16-default-pins { 82 pinctrl-single,pins = < 83 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ 84 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ 85 >; 86 }; 87}; 88 89&wkup_i2c0 { 90 status = "okay"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&wkup_i2c0_pins_default>; 93 clock-frequency = <400000>; 94 95 eeprom@50 { 96 /* CAV24C256WE-GT3 */ 97 compatible = "atmel,24c256"; 98 reg = <0x50>; 99 }; 100}; 101 102&main_i2c0 { 103 status = "okay"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&main_i2c0_pins_default>; 106 clock-frequency = <400000>; 107 108 exp_som: gpio@21 { 109 compatible = "ti,tca6408"; 110 reg = <0x21>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 114 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 115 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", 116 "GPIO_LIN_EN", "CAN_STB"; 117 }; 118}; 119 120&main_mcan16 { 121 status = "okay"; 122 pinctrl-0 = <&main_mcan16_pins_default>; 123 pinctrl-names = "default"; 124 phys = <&transceiver0>; 125}; 126 127&ospi0 { 128 status = "okay"; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 131 132 flash@0 { 133 compatible = "jedec,spi-nor"; 134 reg = <0x0>; 135 spi-tx-bus-width = <8>; 136 spi-rx-bus-width = <8>; 137 spi-max-frequency = <25000000>; 138 cdns,tshsl-ns = <60>; 139 cdns,tsd2d-ns = <60>; 140 cdns,tchsh-ns = <60>; 141 cdns,tslch-ns = <60>; 142 cdns,read-delay = <4>; 143 }; 144}; 145