1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 chipid@43000014 { 38 compatible = "ti,am654-chipid"; 39 reg = <0x00 0x43000014 0x00 0x4>; 40 }; 41 42 mcu_ram: sram@41c00000 { 43 compatible = "mmio-sram"; 44 reg = <0x00 0x41c00000 0x00 0x100000>; 45 ranges = <0x00 0x00 0x41c00000 0x100000>; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 }; 49 50 wkup_pmx0: pinctrl@4301c000 { 51 compatible = "pinctrl-single"; 52 /* Proxy 0 addressing */ 53 reg = <0x00 0x4301c000 0x00 0x178>; 54 #pinctrl-cells = <1>; 55 pinctrl-single,register-width = <32>; 56 pinctrl-single,function-mask = <0xffffffff>; 57 }; 58 59 wkup_gpio_intr: interrupt-controller@42200000 { 60 compatible = "ti,sci-intr"; 61 reg = <0x00 0x42200000 0x00 0x400>; 62 ti,intr-trigger-type = <1>; 63 interrupt-controller; 64 interrupt-parent = <&gic500>; 65 #interrupt-cells = <1>; 66 ti,sci = <&sms>; 67 ti,sci-dev-id = <125>; 68 ti,interrupt-ranges = <16 960 16>; 69 }; 70 71 mcu_conf: syscon@40f00000 { 72 compatible = "syscon", "simple-mfd"; 73 reg = <0x0 0x40f00000 0x0 0x20000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0x0 0x0 0x40f00000 0x20000>; 77 78 phy_gmii_sel: phy@4040 { 79 compatible = "ti,am654-phy-gmii-sel"; 80 reg = <0x4040 0x4>; 81 #phy-cells = <1>; 82 }; 83 84 }; 85 86 wkup_uart0: serial@42300000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x42300000 0x00 0x200>; 89 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 90 current-speed = <115200>; 91 clocks = <&k3_clks 359 3>; 92 clock-names = "fclk"; 93 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 94 status = "disabled"; 95 }; 96 97 mcu_uart0: serial@40a00000 { 98 compatible = "ti,j721e-uart", "ti,am654-uart"; 99 reg = <0x00 0x40a00000 0x00 0x200>; 100 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 101 current-speed = <115200>; 102 clocks = <&k3_clks 149 3>; 103 clock-names = "fclk"; 104 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 105 status = "disabled"; 106 }; 107 108 wkup_gpio0: gpio@42110000 { 109 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 110 reg = <0x00 0x42110000 0x00 0x100>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 interrupt-parent = <&wkup_gpio_intr>; 114 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 115 interrupt-controller; 116 #interrupt-cells = <2>; 117 ti,ngpio = <89>; 118 ti,davinci-gpio-unbanked = <0>; 119 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&k3_clks 115 0>; 121 clock-names = "gpio"; 122 }; 123 124 wkup_gpio1: gpio@42100000 { 125 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 126 reg = <0x00 0x42100000 0x00 0x100>; 127 gpio-controller; 128 #gpio-cells = <2>; 129 interrupt-parent = <&wkup_gpio_intr>; 130 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 ti,ngpio = <89>; 134 ti,davinci-gpio-unbanked = <0>; 135 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 136 clocks = <&k3_clks 116 0>; 137 clock-names = "gpio"; 138 }; 139 140 wkup_i2c0: i2c@42120000 { 141 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 142 reg = <0x00 0x42120000 0x00 0x100>; 143 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clocks = <&k3_clks 223 1>; 147 clock-names = "fck"; 148 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 149 status = "disabled"; 150 }; 151 152 mcu_i2c0: i2c@40b00000 { 153 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 154 reg = <0x00 0x40b00000 0x00 0x100>; 155 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clocks = <&k3_clks 221 1>; 159 clock-names = "fck"; 160 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 161 status = "disabled"; 162 }; 163 164 mcu_i2c1: i2c@40b10000 { 165 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 166 reg = <0x00 0x40b10000 0x00 0x100>; 167 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&k3_clks 222 1>; 171 clock-names = "fck"; 172 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 173 status = "disabled"; 174 }; 175 176 mcu_mcan0: can@40528000 { 177 compatible = "bosch,m_can"; 178 reg = <0x00 0x40528000 0x00 0x200>, 179 <0x00 0x40500000 0x00 0x8000>; 180 reg-names = "m_can", "message_ram"; 181 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 182 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 183 clock-names = "hclk", "cclk"; 184 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "int0", "int1"; 187 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 188 status = "disabled"; 189 }; 190 191 mcu_mcan1: can@40568000 { 192 compatible = "bosch,m_can"; 193 reg = <0x00 0x40568000 0x00 0x200>, 194 <0x00 0x40540000 0x00 0x8000>; 195 reg-names = "m_can", "message_ram"; 196 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 197 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 198 clock-names = "hclk", "cclk"; 199 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-names = "int0", "int1"; 202 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 203 status = "disabled"; 204 }; 205 206 mcu_spi0: spi@40300000 { 207 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 208 reg = <0x00 0x040300000 0x00 0x400>; 209 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 213 clocks = <&k3_clks 347 0>; 214 status = "disabled"; 215 }; 216 217 mcu_spi1: spi@40310000 { 218 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 219 reg = <0x00 0x040310000 0x00 0x400>; 220 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 224 clocks = <&k3_clks 348 0>; 225 status = "disabled"; 226 }; 227 228 mcu_spi2: spi@40320000 { 229 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 230 reg = <0x00 0x040320000 0x00 0x400>; 231 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 235 clocks = <&k3_clks 349 0>; 236 status = "disabled"; 237 }; 238 239 mcu_navss: bus@28380000{ 240 compatible = "simple-mfd"; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 244 dma-coherent; 245 dma-ranges; 246 247 ti,sci-dev-id = <267>; 248 249 mcu_ringacc: ringacc@2b800000 { 250 compatible = "ti,am654-navss-ringacc"; 251 reg = <0x0 0x2b800000 0x0 0x400000>, 252 <0x0 0x2b000000 0x0 0x400000>, 253 <0x0 0x28590000 0x0 0x100>, 254 <0x0 0x2a500000 0x0 0x40000>; 255 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 256 ti,num-rings = <286>; 257 ti,sci-rm-range-gp-rings = <0x1>; 258 ti,sci = <&sms>; 259 ti,sci-dev-id = <272>; 260 msi-parent = <&main_udmass_inta>; 261 }; 262 263 mcu_udmap: dma-controller@285c0000 { 264 compatible = "ti,j721e-navss-mcu-udmap"; 265 reg = <0x0 0x285c0000 0x0 0x100>, 266 <0x0 0x2a800000 0x0 0x40000>, 267 <0x0 0x2aa00000 0x0 0x40000>; 268 reg-names = "gcfg", "rchanrt", "tchanrt"; 269 msi-parent = <&main_udmass_inta>; 270 #dma-cells = <1>; 271 272 ti,sci = <&sms>; 273 ti,sci-dev-id = <273>; 274 ti,ringacc = <&mcu_ringacc>; 275 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 276 <0x0f>; /* TX_HCHAN */ 277 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 278 <0x0b>; /* RX_HCHAN */ 279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 280 }; 281 }; 282 283 mcu_cpsw: ethernet@46000000 { 284 compatible = "ti,j721e-cpsw-nuss"; 285 #address-cells = <2>; 286 #size-cells = <2>; 287 reg = <0x0 0x46000000 0x0 0x200000>; 288 reg-names = "cpsw_nuss"; 289 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 290 dma-coherent; 291 clocks = <&k3_clks 29 28>; 292 clock-names = "fck"; 293 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 294 295 dmas = <&mcu_udmap 0xf000>, 296 <&mcu_udmap 0xf001>, 297 <&mcu_udmap 0xf002>, 298 <&mcu_udmap 0xf003>, 299 <&mcu_udmap 0xf004>, 300 <&mcu_udmap 0xf005>, 301 <&mcu_udmap 0xf006>, 302 <&mcu_udmap 0xf007>, 303 <&mcu_udmap 0x7000>; 304 dma-names = "tx0", "tx1", "tx2", "tx3", 305 "tx4", "tx5", "tx6", "tx7", 306 "rx"; 307 308 ethernet-ports { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 cpsw_port1: port@1 { 313 reg = <1>; 314 ti,mac-only; 315 label = "port1"; 316 ti,syscon-efuse = <&mcu_conf 0x200>; 317 phys = <&phy_gmii_sel 1>; 318 }; 319 }; 320 321 davinci_mdio: mdio@f00 { 322 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 323 reg = <0x0 0xf00 0x0 0x100>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clocks = <&k3_clks 29 28>; 327 clock-names = "fck"; 328 bus_freq = <1000000>; 329 }; 330 331 cpts@3d000 { 332 compatible = "ti,am65-cpts"; 333 reg = <0x0 0x3d000 0x0 0x400>; 334 clocks = <&k3_clks 29 3>; 335 clock-names = "cpts"; 336 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "cpts"; 338 ti,cpts-ext-ts-inputs = <4>; 339 ti,cpts-periodic-outputs = <2>; 340 }; 341 }; 342 343 tscadc0: tscadc@40200000 { 344 compatible = "ti,am3359-tscadc"; 345 reg = <0x00 0x40200000 0x00 0x1000>; 346 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 347 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 348 clocks = <&k3_clks 0 0>; 349 assigned-clocks = <&k3_clks 0 2>; 350 assigned-clock-rates = <60000000>; 351 clock-names = "fck"; 352 dmas = <&main_udmap 0x7400>, 353 <&main_udmap 0x7401>; 354 dma-names = "fifo0", "fifo1"; 355 status = "disabled"; 356 357 adc { 358 #io-channel-cells = <1>; 359 compatible = "ti,am3359-adc"; 360 }; 361 }; 362 363 tscadc1: tscadc@40210000 { 364 compatible = "ti,am3359-tscadc"; 365 reg = <0x00 0x40210000 0x00 0x1000>; 366 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 367 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 1 0>; 369 assigned-clocks = <&k3_clks 1 2>; 370 assigned-clock-rates = <60000000>; 371 clock-names = "fck"; 372 dmas = <&main_udmap 0x7402>, 373 <&main_udmap 0x7403>; 374 dma-names = "fifo0", "fifo1"; 375 status = "disabled"; 376 377 adc { 378 #io-channel-cells = <1>; 379 compatible = "ti,am3359-adc"; 380 }; 381 }; 382}; 383