1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 4G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 28 <0x00000008 0x80000000 0x00000000 0x80000000>; 29 }; 30 31 reserved_memory: reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa4000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa4100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa5000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa5100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa6000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 c66_0_memory_region: c66-memory@a6100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa6100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 127 compatible = "shared-dma-pool"; 128 reg = <0x00 0xa7000000 0x00 0x100000>; 129 no-map; 130 }; 131 132 c66_1_memory_region: c66-memory@a7100000 { 133 compatible = "shared-dma-pool"; 134 reg = <0x00 0xa7100000 0x00 0xf00000>; 135 no-map; 136 }; 137 138 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 139 compatible = "shared-dma-pool"; 140 reg = <0x00 0xa8000000 0x00 0x100000>; 141 no-map; 142 }; 143 144 c71_0_memory_region: c71-memory@a8100000 { 145 compatible = "shared-dma-pool"; 146 reg = <0x00 0xa8100000 0x00 0xf00000>; 147 no-map; 148 }; 149 150 rtos_ipc_memory_region: ipc-memories@aa000000 { 151 reg = <0x00 0xaa000000 0x00 0x01c00000>; 152 alignment = <0x1000>; 153 no-map; 154 }; 155 }; 156 157 vusb_main: fixedregulator-vusb-main5v0 { 158 /* USB MAIN INPUT 5V DC */ 159 compatible = "regulator-fixed"; 160 regulator-name = "vusb-main5v0"; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 regulator-always-on; 164 regulator-boot-on; 165 }; 166 167 vsys_3v3: fixedregulator-vsys3v3 { 168 /* Output of LM5141 */ 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_3v3"; 171 regulator-min-microvolt = <3300000>; 172 regulator-max-microvolt = <3300000>; 173 vin-supply = <&vusb_main>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vdd_mmc1: fixedregulator-sd { 179 compatible = "regulator-fixed"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 182 regulator-name = "vdd_mmc1"; 183 regulator-min-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 enable-active-high; 187 vin-supply = <&vsys_3v3>; 188 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 189 }; 190 191 vdd_sd_dv_alt: gpio-regulator-tps659411 { 192 compatible = "regulator-gpio"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 195 regulator-name = "tps659411"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 regulator-boot-on; 199 vin-supply = <&vsys_3v3>; 200 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 201 states = <1800000 0x0>, 202 <3300000 0x1>; 203 }; 204 205 dp_pwr_3v3: fixedregulator-dp-prw { 206 compatible = "regulator-fixed"; 207 regulator-name = "dp-pwr"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&dp_pwr_en_pins_default>; 212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 213 enable-active-high; 214 }; 215 216 dp0: connector { 217 compatible = "dp-connector"; 218 label = "DP0"; 219 type = "full-size"; 220 dp-pwr-supply = <&dp_pwr_3v3>; 221 222 port { 223 dp_connector_in: endpoint { 224 remote-endpoint = <&dp0_out>; 225 }; 226 }; 227 }; 228 229 hdmi-connector { 230 compatible = "hdmi-connector"; 231 label = "hdmi"; 232 type = "a"; 233 234 pinctrl-names = "default"; 235 pinctrl-0 = <&hdmi_hpd_pins_default>; 236 237 ddc-i2c-bus = <&main_i2c1>; 238 239 /* HDMI_HPD */ 240 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 241 242 port { 243 hdmi_connector_in: endpoint { 244 remote-endpoint = <&tfp410_out>; 245 }; 246 }; 247 }; 248 249 dvi-bridge { 250 compatible = "ti,tfp410"; 251 252 pinctrl-names = "default"; 253 pinctrl-0 = <&hdmi_pdn_pins_default>; 254 255 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 256 ti,deskew = <0>; 257 258 ports { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 port@0 { 263 reg = <0>; 264 265 tfp410_in: endpoint { 266 remote-endpoint = <&dpi1_out>; 267 pclk-sample = <1>; 268 }; 269 }; 270 271 port@1 { 272 reg = <1>; 273 274 tfp410_out: endpoint { 275 remote-endpoint = 276 <&hdmi_connector_in>; 277 }; 278 }; 279 }; 280 }; 281}; 282 283&main_pmx0 { 284 main_mmc1_pins_default: main-mmc1-pins-default { 285 pinctrl-single,pins = < 286 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 287 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 288 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 289 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 290 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 291 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 292 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 293 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 294 >; 295 }; 296 297 main_uart0_pins_default: main-uart0-pins-default { 298 pinctrl-single,pins = < 299 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 300 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 301 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 302 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 303 >; 304 }; 305 306 main_i2c0_pins_default: main-i2c0-pins-default { 307 pinctrl-single,pins = < 308 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 309 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 310 >; 311 }; 312 313 main_i2c1_pins_default: main-i2c1-pins-default { 314 pinctrl-single,pins = < 315 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 316 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 317 >; 318 }; 319 320 main_i2c3_pins_default: main-i2c3-pins-default { 321 pinctrl-single,pins = < 322 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 323 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 324 >; 325 }; 326 327 main_usbss0_pins_default: main-usbss0-pins-default { 328 pinctrl-single,pins = < 329 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 330 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 331 >; 332 }; 333 334 main_usbss1_pins_default: main-usbss1-pins-default { 335 pinctrl-single,pins = < 336 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 337 >; 338 }; 339 340 dp0_pins_default: dp0-pins-default { 341 pinctrl-single,pins = < 342 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 343 >; 344 }; 345 346 dp_pwr_en_pins_default: dp-pwr-en-pins-default { 347 pinctrl-single,pins = < 348 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 349 >; 350 }; 351 352 dss_vout0_pins_default: dss-vout0-pins-default { 353 pinctrl-single,pins = < 354 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 355 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 356 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 357 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 358 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 359 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 360 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 361 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 362 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 363 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 364 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 365 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 366 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 367 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 368 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 369 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 370 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 371 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 372 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 373 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 374 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 375 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 376 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 377 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 378 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 379 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 380 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 381 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 382 >; 383 }; 384 385 hdmi_hpd_pins_default: hdmi-hpd-pins-default { 386 pinctrl-single,pins = < 387 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 388 >; 389 }; 390 391 hdmi_pdn_pins_default: hdmi-pdn-pins-default { 392 pinctrl-single,pins = < 393 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 394 >; 395 }; 396 397 /* Reset for M.2 E Key slot on PCIe0 */ 398 ekey_reset_pins_default: ekey-reset-pns-pins-default { 399 pinctrl-single,pins = < 400 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 401 >; 402 }; 403}; 404 405&wkup_pmx0 { 406 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 407 pinctrl-single,pins = < 408 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 409 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 410 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 411 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 412 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 413 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 414 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 415 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 416 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 417 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 418 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 419 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 420 >; 421 }; 422 423 mcu_mdio_pins_default: mcu-mdio1-pins-default { 424 pinctrl-single,pins = < 425 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 426 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 427 >; 428 }; 429 430 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 431 pinctrl-single,pins = < 432 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 433 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 434 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 435 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 436 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 437 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 438 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 439 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 440 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 441 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 442 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 443 >; 444 }; 445 446 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { 447 pinctrl-single,pins = < 448 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 449 >; 450 }; 451 452 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 453 pinctrl-single,pins = < 454 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 455 >; 456 }; 457 458 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 459 pinctrl-single,pins = < 460 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 461 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 462 >; 463 }; 464 465 /* Reset for M.2 M Key slot on PCIe1 */ 466 mkey_reset_pins_default: mkey-reset-pns-pins-default { 467 pinctrl-single,pins = < 468 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 469 >; 470 }; 471}; 472 473&wkup_uart0 { 474 /* Wakeup UART is used by System firmware */ 475 status = "reserved"; 476}; 477 478&main_uart0 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&main_uart0_pins_default>; 481 /* Shared with ATF on this platform */ 482 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 483}; 484 485&main_uart2 { 486 /* Brought out on RPi header */ 487 status = "disabled"; 488}; 489 490&main_uart3 { 491 /* UART not brought out */ 492 status = "disabled"; 493}; 494 495&main_uart5 { 496 /* UART not brought out */ 497 status = "disabled"; 498}; 499 500&main_uart6 { 501 /* UART not brought out */ 502 status = "disabled"; 503}; 504 505&main_uart7 { 506 /* UART not brought out */ 507 status = "disabled"; 508}; 509 510&main_uart8 { 511 /* UART not brought out */ 512 status = "disabled"; 513}; 514 515&main_uart9 { 516 /* Brought out on M.2 E Key */ 517 status = "disabled"; 518}; 519 520&main_sdhci0 { 521 /* Unused */ 522 status = "disabled"; 523}; 524 525&main_sdhci1 { 526 /* SD Card */ 527 vmmc-supply = <&vdd_mmc1>; 528 vqmmc-supply = <&vdd_sd_dv_alt>; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&main_mmc1_pins_default>; 531 ti,driver-strength-ohm = <50>; 532 disable-wp; 533}; 534 535&main_sdhci2 { 536 /* Unused */ 537 status = "disabled"; 538}; 539 540&ospi0 { 541 pinctrl-names = "default"; 542 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 543 544 flash@0 { 545 compatible = "jedec,spi-nor"; 546 reg = <0x0>; 547 spi-tx-bus-width = <8>; 548 spi-rx-bus-width = <8>; 549 spi-max-frequency = <25000000>; 550 cdns,tshsl-ns = <60>; 551 cdns,tsd2d-ns = <60>; 552 cdns,tchsh-ns = <60>; 553 cdns,tslch-ns = <60>; 554 cdns,read-delay = <4>; 555 }; 556}; 557 558&ospi1 { 559 /* Unused */ 560 status = "disabled"; 561}; 562 563&main_i2c0 { 564 pinctrl-names = "default"; 565 pinctrl-0 = <&main_i2c0_pins_default>; 566 clock-frequency = <400000>; 567 568 i2c-mux@71 { 569 compatible = "nxp,pca9543"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 reg = <0x71>; 573 574 /* PCIe1 M.2 M Key I2C */ 575 i2c@0 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0>; 579 }; 580 581 /* PCIe0 M.2 E Key I2C */ 582 i2c@1 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 reg = <1>; 586 }; 587 }; 588}; 589 590&main_i2c1 { 591 pinctrl-names = "default"; 592 pinctrl-0 = <&main_i2c1_pins_default>; 593 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 594 clock-frequency = <100000>; 595}; 596 597&main_i2c2 { 598 /* Unused */ 599 status = "disabled"; 600}; 601 602&main_i2c3 { 603 pinctrl-names = "default"; 604 pinctrl-0 = <&main_i2c3_pins_default>; 605 clock-frequency = <400000>; 606 607 i2c-mux@70 { 608 compatible = "nxp,pca9543"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <0x70>; 612 613 /* CSI0 I2C */ 614 i2c@0 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 reg = <0>; 618 }; 619 620 /* CSI1 I2C */ 621 i2c@1 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <1>; 625 }; 626 }; 627}; 628 629&main_i2c4 { 630 /* Unused */ 631 status = "disabled"; 632}; 633 634&main_i2c5 { 635 /* Brought out on RPi Header */ 636 status = "disabled"; 637}; 638 639&main_i2c6 { 640 /* Unused */ 641 status = "disabled"; 642}; 643 644&main_gpio2 { 645 status = "disabled"; 646}; 647 648&main_gpio3 { 649 status = "disabled"; 650}; 651 652&main_gpio4 { 653 status = "disabled"; 654}; 655 656&main_gpio5 { 657 status = "disabled"; 658}; 659 660&main_gpio6 { 661 status = "disabled"; 662}; 663 664&main_gpio7 { 665 status = "disabled"; 666}; 667 668&wkup_gpio1 { 669 status = "disabled"; 670}; 671 672&main_r5fss0_core0{ 673 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; 674}; 675 676&usb_serdes_mux { 677 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 678}; 679 680&serdes_ln_ctrl { 681 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 682 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 683 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 684 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 685 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 686 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 687}; 688 689&serdes_wiz3 { 690 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 691 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 692}; 693 694&serdes3 { 695 serdes3_usb_link: phy@0 { 696 reg = <0>; 697 cdns,num-lanes = <2>; 698 #phy-cells = <0>; 699 cdns,phy-type = <PHY_TYPE_USB3>; 700 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 701 }; 702}; 703 704&serdes4 { 705 torrent_phy_dp: phy@0 { 706 reg = <0>; 707 resets = <&serdes_wiz4 1>; 708 cdns,phy-type = <PHY_TYPE_DP>; 709 cdns,num-lanes = <4>; 710 cdns,max-bit-rate = <5400>; 711 #phy-cells = <0>; 712 }; 713}; 714 715&mhdp { 716 phys = <&torrent_phy_dp>; 717 phy-names = "dpphy"; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&dp0_pins_default>; 720}; 721 722&usbss0 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&main_usbss0_pins_default>; 725 ti,vbus-divider; 726}; 727 728&usb0 { 729 dr_mode = "otg"; 730 maximum-speed = "super-speed"; 731 phys = <&serdes3_usb_link>; 732 phy-names = "cdns3,usb3-phy"; 733}; 734 735&serdes2 { 736 serdes2_usb_link: phy@1 { 737 reg = <1>; 738 cdns,num-lanes = <1>; 739 #phy-cells = <0>; 740 cdns,phy-type = <PHY_TYPE_USB3>; 741 resets = <&serdes_wiz2 2>; 742 }; 743}; 744 745&usbss1 { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&main_usbss1_pins_default>; 748 ti,vbus-divider; 749}; 750 751&usb1 { 752 dr_mode = "host"; 753 maximum-speed = "super-speed"; 754 phys = <&serdes2_usb_link>; 755 phy-names = "cdns3,usb3-phy"; 756}; 757 758&tscadc0 { 759 /* Unused */ 760 status = "disabled"; 761}; 762 763&tscadc1 { 764 /* Unused */ 765 status = "disabled"; 766}; 767 768&mcu_cpsw { 769 pinctrl-names = "default"; 770 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 771}; 772 773&davinci_mdio { 774 phy0: ethernet-phy@0 { 775 reg = <0>; 776 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 777 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 778 }; 779}; 780 781&cpsw_port1 { 782 phy-mode = "rgmii-rxid"; 783 phy-handle = <&phy0>; 784}; 785 786&dss { 787 pinctrl-names = "default"; 788 pinctrl-0 = <&dss_vout0_pins_default>; 789 790 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 791 <&k3_clks 152 4>, /* VP 2 pixel clock */ 792 <&k3_clks 152 9>, /* VP 3 pixel clock */ 793 <&k3_clks 152 13>; /* VP 4 pixel clock */ 794 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 795 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 796 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 797 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 798}; 799 800&dss_ports { 801 #address-cells = <1>; 802 #size-cells = <0>; 803 804 port@0 { 805 reg = <0>; 806 807 dpi0_out: endpoint { 808 remote-endpoint = <&dp0_in>; 809 }; 810 }; 811 812 port@1 { 813 reg = <1>; 814 815 dpi1_out: endpoint { 816 remote-endpoint = <&tfp410_in>; 817 }; 818 }; 819}; 820 821&dp0_ports { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 825 port@0 { 826 reg = <0>; 827 dp0_in: endpoint { 828 remote-endpoint = <&dpi0_out>; 829 }; 830 }; 831 832 port@4 { 833 reg = <4>; 834 dp0_out: endpoint { 835 remote-endpoint = <&dp_connector_in>; 836 }; 837 }; 838}; 839 840&mcasp0 { 841 /* Unused */ 842 status = "disabled"; 843}; 844 845&mcasp1 { 846 /* Unused */ 847 status = "disabled"; 848}; 849 850&mcasp2 { 851 /* Unused */ 852 status = "disabled"; 853}; 854 855&mcasp3 { 856 /* Unused */ 857 status = "disabled"; 858}; 859 860&mcasp4 { 861 /* Unused */ 862 status = "disabled"; 863}; 864 865&mcasp5 { 866 /* Unused */ 867 status = "disabled"; 868}; 869 870&mcasp6 { 871 /* Brought out on RPi header */ 872 status = "disabled"; 873}; 874 875&mcasp7 { 876 /* Unused */ 877 status = "disabled"; 878}; 879 880&mcasp8 { 881 /* Unused */ 882 status = "disabled"; 883}; 884 885&mcasp9 { 886 /* Unused */ 887 status = "disabled"; 888}; 889 890&mcasp10 { 891 /* Unused */ 892 status = "disabled"; 893}; 894 895&mcasp11 { 896 /* Brought out on M.2 E Key */ 897 status = "disabled"; 898}; 899 900&serdes0 { 901 serdes0_pcie_link: phy@0 { 902 reg = <0>; 903 cdns,num-lanes = <1>; 904 #phy-cells = <0>; 905 cdns,phy-type = <PHY_TYPE_PCIE>; 906 resets = <&serdes_wiz0 1>; 907 }; 908}; 909 910&serdes1 { 911 serdes1_pcie_link: phy@0 { 912 reg = <0>; 913 cdns,num-lanes = <2>; 914 #phy-cells = <0>; 915 cdns,phy-type = <PHY_TYPE_PCIE>; 916 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 917 }; 918}; 919 920&pcie0_rc { 921 pinctrl-names = "default"; 922 pinctrl-0 = <&ekey_reset_pins_default>; 923 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 924 925 phys = <&serdes0_pcie_link>; 926 phy-names = "pcie-phy"; 927 num-lanes = <1>; 928}; 929 930&pcie1_rc { 931 pinctrl-names = "default"; 932 pinctrl-0 = <&mkey_reset_pins_default>; 933 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 934 935 phys = <&serdes1_pcie_link>; 936 phy-names = "pcie-phy"; 937 num-lanes = <2>; 938}; 939 940&pcie2_rc { 941 /* Unused */ 942 status = "disabled"; 943}; 944 945&pcie0_ep { 946 status = "disabled"; 947 phys = <&serdes0_pcie_link>; 948 phy-names = "pcie-phy"; 949 num-lanes = <1>; 950}; 951 952&pcie1_ep { 953 status = "disabled"; 954 phys = <&serdes1_pcie_link>; 955 phy-names = "pcie-phy"; 956 num-lanes = <2>; 957}; 958 959&pcie2_ep { 960 /* Unused */ 961 status = "disabled"; 962}; 963 964&pcie3_rc { 965 /* Unused */ 966 status = "disabled"; 967}; 968 969&pcie3_ep { 970 /* Unused */ 971 status = "disabled"; 972}; 973 974&icssg0_mdio { 975 status = "disabled"; 976}; 977 978&icssg1_mdio { 979 status = "disabled"; 980}; 981 982&ufs_wrapper { 983 status = "disabled"; 984}; 985 986&mailbox0_cluster0 { 987 interrupts = <436>; 988 989 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 990 ti,mbox-rx = <0 0 0>; 991 ti,mbox-tx = <1 0 0>; 992 }; 993 994 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 995 ti,mbox-rx = <2 0 0>; 996 ti,mbox-tx = <3 0 0>; 997 }; 998}; 999 1000&mailbox0_cluster1 { 1001 interrupts = <432>; 1002 1003 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1004 ti,mbox-rx = <0 0 0>; 1005 ti,mbox-tx = <1 0 0>; 1006 }; 1007 1008 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1009 ti,mbox-rx = <2 0 0>; 1010 ti,mbox-tx = <3 0 0>; 1011 }; 1012}; 1013 1014&mailbox0_cluster2 { 1015 interrupts = <428>; 1016 1017 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1018 ti,mbox-rx = <0 0 0>; 1019 ti,mbox-tx = <1 0 0>; 1020 }; 1021 1022 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1023 ti,mbox-rx = <2 0 0>; 1024 ti,mbox-tx = <3 0 0>; 1025 }; 1026}; 1027 1028&mailbox0_cluster3 { 1029 interrupts = <424>; 1030 1031 mbox_c66_0: mbox-c66-0 { 1032 ti,mbox-rx = <0 0 0>; 1033 ti,mbox-tx = <1 0 0>; 1034 }; 1035 1036 mbox_c66_1: mbox-c66-1 { 1037 ti,mbox-rx = <2 0 0>; 1038 ti,mbox-tx = <3 0 0>; 1039 }; 1040}; 1041 1042&mailbox0_cluster4 { 1043 interrupts = <420>; 1044 1045 mbox_c71_0: mbox-c71-0 { 1046 ti,mbox-rx = <0 0 0>; 1047 ti,mbox-tx = <1 0 0>; 1048 }; 1049}; 1050 1051&mailbox0_cluster5 { 1052 status = "disabled"; 1053}; 1054 1055&mailbox0_cluster6 { 1056 status = "disabled"; 1057}; 1058 1059&mailbox0_cluster7 { 1060 status = "disabled"; 1061}; 1062 1063&mailbox0_cluster8 { 1064 status = "disabled"; 1065}; 1066 1067&mailbox0_cluster9 { 1068 status = "disabled"; 1069}; 1070 1071&mailbox0_cluster10 { 1072 status = "disabled"; 1073}; 1074 1075&mailbox0_cluster11 { 1076 status = "disabled"; 1077}; 1078 1079&mcu_r5fss0_core0 { 1080 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1081 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1082 <&mcu_r5fss0_core0_memory_region>; 1083}; 1084 1085&mcu_r5fss0_core1 { 1086 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1087 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1088 <&mcu_r5fss0_core1_memory_region>; 1089}; 1090 1091&main_r5fss0_core0 { 1092 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1093 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1094 <&main_r5fss0_core0_memory_region>; 1095}; 1096 1097&main_r5fss0_core1 { 1098 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1099 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1100 <&main_r5fss0_core1_memory_region>; 1101}; 1102 1103&main_r5fss1_core0 { 1104 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1105 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1106 <&main_r5fss1_core0_memory_region>; 1107}; 1108 1109&main_r5fss1_core1 { 1110 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1111 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1112 <&main_r5fss1_core1_memory_region>; 1113}; 1114 1115&c66_0 { 1116 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1117 memory-region = <&c66_0_dma_memory_region>, 1118 <&c66_0_memory_region>; 1119}; 1120 1121&c66_1 { 1122 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1123 memory-region = <&c66_1_dma_memory_region>, 1124 <&c66_1_memory_region>; 1125}; 1126 1127&c71_0 { 1128 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1129 memory-region = <&c71_0_dma_memory_region>, 1130 <&c71_0_memory_region>; 1131}; 1132