1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 mcu_ram: sram@41c00000 { 66 compatible = "mmio-sram"; 67 reg = <0x00 0x41c00000 0x00 0x100000>; 68 ranges = <0x0 0x00 0x41c00000 0x100000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 73 wkup_uart0: serial@42300000 { 74 compatible = "ti,j721e-uart", "ti,am654-uart"; 75 reg = <0x00 0x42300000 0x00 0x100>; 76 reg-shift = <2>; 77 reg-io-width = <4>; 78 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 79 clock-frequency = <48000000>; 80 current-speed = <115200>; 81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 82 clocks = <&k3_clks 287 0>; 83 clock-names = "fclk"; 84 }; 85 86 mcu_uart0: serial@40a00000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x40a00000 0x00 0x100>; 89 reg-shift = <2>; 90 reg-io-width = <4>; 91 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 92 clock-frequency = <96000000>; 93 current-speed = <115200>; 94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&k3_clks 149 0>; 96 clock-names = "fclk"; 97 }; 98 99 wkup_gpio_intr: interrupt-controller2 { 100 compatible = "ti,sci-intr"; 101 ti,intr-trigger-type = <1>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 #interrupt-cells = <1>; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <137>; 107 ti,interrupt-ranges = <16 960 16>; 108 }; 109 110 wkup_gpio0: gpio@42110000 { 111 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 112 reg = <0x0 0x42110000 0x0 0x100>; 113 gpio-controller; 114 #gpio-cells = <2>; 115 interrupt-parent = <&wkup_gpio_intr>; 116 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 117 interrupt-controller; 118 #interrupt-cells = <2>; 119 ti,ngpio = <84>; 120 ti,davinci-gpio-unbanked = <0>; 121 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&k3_clks 113 0>; 123 clock-names = "gpio"; 124 }; 125 126 wkup_gpio1: gpio@42100000 { 127 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 128 reg = <0x0 0x42100000 0x0 0x100>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-parent = <&wkup_gpio_intr>; 132 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 ti,ngpio = <84>; 136 ti,davinci-gpio-unbanked = <0>; 137 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 138 clocks = <&k3_clks 114 0>; 139 clock-names = "gpio"; 140 }; 141 142 mcu_i2c0: i2c@40b00000 { 143 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 144 reg = <0x0 0x40b00000 0x0 0x100>; 145 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "fck"; 149 clocks = <&k3_clks 194 0>; 150 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 151 }; 152 153 mcu_i2c1: i2c@40b10000 { 154 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 155 reg = <0x0 0x40b10000 0x0 0x100>; 156 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "fck"; 160 clocks = <&k3_clks 195 0>; 161 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 162 }; 163 164 wkup_i2c0: i2c@42120000 { 165 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 166 reg = <0x0 0x42120000 0x0 0x100>; 167 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clock-names = "fck"; 171 clocks = <&k3_clks 197 0>; 172 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 173 }; 174 175 fss: fss@47000000 { 176 compatible = "simple-bus"; 177 reg = <0x0 0x47000000 0x0 0x100>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 ospi0: spi@47040000 { 183 compatible = "ti,am654-ospi"; 184 reg = <0x0 0x47040000 0x0 0x100>, 185 <0x5 0x00000000 0x1 0x0000000>; 186 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 187 cdns,fifo-depth = <256>; 188 cdns,fifo-width = <4>; 189 cdns,trigger-address = <0x0>; 190 clocks = <&k3_clks 103 0>; 191 assigned-clocks = <&k3_clks 103 0>; 192 assigned-clock-parents = <&k3_clks 103 2>; 193 assigned-clock-rates = <166666666>; 194 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 }; 198 199 ospi1: spi@47050000 { 200 compatible = "ti,am654-ospi"; 201 reg = <0x0 0x47050000 0x0 0x100>, 202 <0x7 0x00000000 0x1 0x00000000>; 203 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 204 cdns,fifo-depth = <256>; 205 cdns,fifo-width = <4>; 206 cdns,trigger-address = <0x0>; 207 clocks = <&k3_clks 104 0>; 208 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 }; 212 }; 213 214 tscadc0: tscadc@40200000 { 215 compatible = "ti,am3359-tscadc"; 216 reg = <0x0 0x40200000 0x0 0x1000>; 217 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 218 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 219 clocks = <&k3_clks 0 1>; 220 assigned-clocks = <&k3_clks 0 3>; 221 assigned-clock-rates = <60000000>; 222 clock-names = "adc_tsc_fck"; 223 dmas = <&main_udmap 0x7400>, 224 <&main_udmap 0x7401>; 225 dma-names = "fifo0", "fifo1"; 226 227 adc { 228 #io-channel-cells = <1>; 229 compatible = "ti,am3359-adc"; 230 }; 231 }; 232 233 tscadc1: tscadc@40210000 { 234 compatible = "ti,am3359-tscadc"; 235 reg = <0x0 0x40210000 0x0 0x1000>; 236 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 237 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 238 clocks = <&k3_clks 1 1>; 239 assigned-clocks = <&k3_clks 1 3>; 240 assigned-clock-rates = <60000000>; 241 clock-names = "adc_tsc_fck"; 242 dmas = <&main_udmap 0x7402>, 243 <&main_udmap 0x7403>; 244 dma-names = "fifo0", "fifo1"; 245 246 adc { 247 #io-channel-cells = <1>; 248 compatible = "ti,am3359-adc"; 249 }; 250 }; 251 252 mcu-navss { 253 compatible = "simple-mfd"; 254 #address-cells = <2>; 255 #size-cells = <2>; 256 ranges; 257 dma-coherent; 258 dma-ranges; 259 260 ti,sci-dev-id = <232>; 261 262 mcu_ringacc: ringacc@2b800000 { 263 compatible = "ti,am654-navss-ringacc"; 264 reg = <0x0 0x2b800000 0x0 0x400000>, 265 <0x0 0x2b000000 0x0 0x400000>, 266 <0x0 0x28590000 0x0 0x100>, 267 <0x0 0x2a500000 0x0 0x40000>; 268 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 269 ti,num-rings = <286>; 270 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 271 ti,sci = <&dmsc>; 272 ti,sci-dev-id = <235>; 273 msi-parent = <&main_udmass_inta>; 274 }; 275 276 mcu_udmap: dma-controller@285c0000 { 277 compatible = "ti,j721e-navss-mcu-udmap"; 278 reg = <0x0 0x285c0000 0x0 0x100>, 279 <0x0 0x2a800000 0x0 0x40000>, 280 <0x0 0x2aa00000 0x0 0x40000>; 281 reg-names = "gcfg", "rchanrt", "tchanrt"; 282 msi-parent = <&main_udmass_inta>; 283 #dma-cells = <1>; 284 285 ti,sci = <&dmsc>; 286 ti,sci-dev-id = <236>; 287 ti,ringacc = <&mcu_ringacc>; 288 289 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 290 <0x0f>; /* TX_HCHAN */ 291 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 292 <0x0b>; /* RX_HCHAN */ 293 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 294 }; 295 }; 296 297 mcu_cpsw: ethernet@46000000 { 298 compatible = "ti,j721e-cpsw-nuss"; 299 #address-cells = <2>; 300 #size-cells = <2>; 301 reg = <0x0 0x46000000 0x0 0x200000>; 302 reg-names = "cpsw_nuss"; 303 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 304 dma-coherent; 305 clocks = <&k3_clks 18 22>; 306 clock-names = "fck"; 307 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 308 309 dmas = <&mcu_udmap 0xf000>, 310 <&mcu_udmap 0xf001>, 311 <&mcu_udmap 0xf002>, 312 <&mcu_udmap 0xf003>, 313 <&mcu_udmap 0xf004>, 314 <&mcu_udmap 0xf005>, 315 <&mcu_udmap 0xf006>, 316 <&mcu_udmap 0xf007>, 317 <&mcu_udmap 0x7000>; 318 dma-names = "tx0", "tx1", "tx2", "tx3", 319 "tx4", "tx5", "tx6", "tx7", 320 "rx"; 321 322 ethernet-ports { 323 #address-cells = <1>; 324 #size-cells = <0>; 325 326 cpsw_port1: port@1 { 327 reg = <1>; 328 ti,mac-only; 329 label = "port1"; 330 ti,syscon-efuse = <&mcu_conf 0x200>; 331 phys = <&phy_gmii_sel 1>; 332 }; 333 }; 334 335 davinci_mdio: mdio@f00 { 336 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 337 reg = <0x0 0xf00 0x0 0x100>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clocks = <&k3_clks 18 22>; 341 clock-names = "fck"; 342 bus_freq = <1000000>; 343 }; 344 345 cpts@3d000 { 346 compatible = "ti,am65-cpts"; 347 reg = <0x0 0x3d000 0x0 0x400>; 348 clocks = <&k3_clks 18 2>; 349 clock-names = "cpts"; 350 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-names = "cpts"; 352 ti,cpts-ext-ts-inputs = <4>; 353 ti,cpts-periodic-outputs = <2>; 354 }; 355 }; 356}; 357