1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11&cbass_main { 12 msmc_ram: sram@70000000 { 13 compatible = "mmio-sram"; 14 reg = <0x0 0x70000000 0x0 0x800000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x0 0x0 0x70000000 0x800000>; 18 19 atf-sram@0 { 20 reg = <0x0 0x20000>; 21 }; 22 }; 23 24 scm_conf: scm-conf@100000 { 25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x0 0x0 0x00100000 0x1c000>; 30 31 pcie0_ctrl: syscon@4070 { 32 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 33 reg = <0x00004070 0x4>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 ranges = <0x4070 0x4070 0x4>; 37 }; 38 39 pcie1_ctrl: syscon@4074 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0x00004074 0x4>; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x4074 0x4074 0x4>; 45 }; 46 47 pcie2_ctrl: syscon@4078 { 48 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 49 reg = <0x00004078 0x4>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges = <0x4078 0x4078 0x4>; 53 }; 54 55 pcie3_ctrl: syscon@407c { 56 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 57 reg = <0x0000407c 0x4>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges = <0x407c 0x407c 0x4>; 61 }; 62 63 serdes_ln_ctrl: mux@4080 { 64 compatible = "mmio-mux"; 65 reg = <0x00004080 0x50>; 66 #mux-control-cells = <1>; 67 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 68 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 69 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 70 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 71 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 72 /* SERDES4 lane0/1/2/3 select */ 73 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 74 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 75 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 76 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 77 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 78 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 79 }; 80 81 usb_serdes_mux: mux-controller@4000 { 82 compatible = "mmio-mux"; 83 #mux-control-cells = <1>; 84 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 85 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 86 }; 87 }; 88 89 gic500: interrupt-controller@1800000 { 90 compatible = "arm,gic-v3"; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 #interrupt-cells = <3>; 95 interrupt-controller; 96 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 97 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 98 99 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 101 102 gic_its: msi-controller@1820000 { 103 compatible = "arm,gic-v3-its"; 104 reg = <0x00 0x01820000 0x00 0x10000>; 105 socionext,synquacer-pre-its = <0x1000000 0x400000>; 106 msi-controller; 107 #msi-cells = <1>; 108 }; 109 }; 110 111 main_gpio_intr: interrupt-controller0 { 112 compatible = "ti,sci-intr"; 113 ti,intr-trigger-type = <1>; 114 interrupt-controller; 115 interrupt-parent = <&gic500>; 116 #interrupt-cells = <1>; 117 ti,sci = <&dmsc>; 118 ti,sci-dev-id = <131>; 119 ti,interrupt-ranges = <8 392 56>; 120 }; 121 122 main-navss { 123 compatible = "simple-mfd"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 dma-coherent; 128 dma-ranges; 129 130 ti,sci-dev-id = <199>; 131 132 main_navss_intr: interrupt-controller1 { 133 compatible = "ti,sci-intr"; 134 ti,intr-trigger-type = <4>; 135 interrupt-controller; 136 interrupt-parent = <&gic500>; 137 #interrupt-cells = <1>; 138 ti,sci = <&dmsc>; 139 ti,sci-dev-id = <213>; 140 ti,interrupt-ranges = <0 64 64>, 141 <64 448 64>, 142 <128 672 64>; 143 }; 144 145 main_udmass_inta: interrupt-controller@33d00000 { 146 compatible = "ti,sci-inta"; 147 reg = <0x0 0x33d00000 0x0 0x100000>; 148 interrupt-controller; 149 interrupt-parent = <&main_navss_intr>; 150 msi-controller; 151 ti,sci = <&dmsc>; 152 ti,sci-dev-id = <209>; 153 ti,interrupt-ranges = <0 0 256>; 154 }; 155 156 secure_proxy_main: mailbox@32c00000 { 157 compatible = "ti,am654-secure-proxy"; 158 #mbox-cells = <1>; 159 reg-names = "target_data", "rt", "scfg"; 160 reg = <0x00 0x32c00000 0x00 0x100000>, 161 <0x00 0x32400000 0x00 0x100000>, 162 <0x00 0x32800000 0x00 0x100000>; 163 interrupt-names = "rx_011"; 164 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 165 }; 166 167 smmu0: iommu@36600000 { 168 compatible = "arm,smmu-v3"; 169 reg = <0x0 0x36600000 0x0 0x100000>; 170 interrupt-parent = <&gic500>; 171 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 172 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 173 interrupt-names = "eventq", "gerror"; 174 #iommu-cells = <1>; 175 }; 176 177 hwspinlock: spinlock@30e00000 { 178 compatible = "ti,am654-hwspinlock"; 179 reg = <0x00 0x30e00000 0x00 0x1000>; 180 #hwlock-cells = <1>; 181 }; 182 183 mailbox0_cluster0: mailbox@31f80000 { 184 compatible = "ti,am654-mailbox"; 185 reg = <0x00 0x31f80000 0x00 0x200>; 186 #mbox-cells = <1>; 187 ti,mbox-num-users = <4>; 188 ti,mbox-num-fifos = <16>; 189 interrupt-parent = <&main_navss_intr>; 190 }; 191 192 mailbox0_cluster1: mailbox@31f81000 { 193 compatible = "ti,am654-mailbox"; 194 reg = <0x00 0x31f81000 0x00 0x200>; 195 #mbox-cells = <1>; 196 ti,mbox-num-users = <4>; 197 ti,mbox-num-fifos = <16>; 198 interrupt-parent = <&main_navss_intr>; 199 }; 200 201 mailbox0_cluster2: mailbox@31f82000 { 202 compatible = "ti,am654-mailbox"; 203 reg = <0x00 0x31f82000 0x00 0x200>; 204 #mbox-cells = <1>; 205 ti,mbox-num-users = <4>; 206 ti,mbox-num-fifos = <16>; 207 interrupt-parent = <&main_navss_intr>; 208 }; 209 210 mailbox0_cluster3: mailbox@31f83000 { 211 compatible = "ti,am654-mailbox"; 212 reg = <0x00 0x31f83000 0x00 0x200>; 213 #mbox-cells = <1>; 214 ti,mbox-num-users = <4>; 215 ti,mbox-num-fifos = <16>; 216 interrupt-parent = <&main_navss_intr>; 217 }; 218 219 mailbox0_cluster4: mailbox@31f84000 { 220 compatible = "ti,am654-mailbox"; 221 reg = <0x00 0x31f84000 0x00 0x200>; 222 #mbox-cells = <1>; 223 ti,mbox-num-users = <4>; 224 ti,mbox-num-fifos = <16>; 225 interrupt-parent = <&main_navss_intr>; 226 }; 227 228 mailbox0_cluster5: mailbox@31f85000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f85000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 }; 236 237 mailbox0_cluster6: mailbox@31f86000 { 238 compatible = "ti,am654-mailbox"; 239 reg = <0x00 0x31f86000 0x00 0x200>; 240 #mbox-cells = <1>; 241 ti,mbox-num-users = <4>; 242 ti,mbox-num-fifos = <16>; 243 interrupt-parent = <&main_navss_intr>; 244 }; 245 246 mailbox0_cluster7: mailbox@31f87000 { 247 compatible = "ti,am654-mailbox"; 248 reg = <0x00 0x31f87000 0x00 0x200>; 249 #mbox-cells = <1>; 250 ti,mbox-num-users = <4>; 251 ti,mbox-num-fifos = <16>; 252 interrupt-parent = <&main_navss_intr>; 253 }; 254 255 mailbox0_cluster8: mailbox@31f88000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f88000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 }; 263 264 mailbox0_cluster9: mailbox@31f89000 { 265 compatible = "ti,am654-mailbox"; 266 reg = <0x00 0x31f89000 0x00 0x200>; 267 #mbox-cells = <1>; 268 ti,mbox-num-users = <4>; 269 ti,mbox-num-fifos = <16>; 270 interrupt-parent = <&main_navss_intr>; 271 }; 272 273 mailbox0_cluster10: mailbox@31f8a000 { 274 compatible = "ti,am654-mailbox"; 275 reg = <0x00 0x31f8a000 0x00 0x200>; 276 #mbox-cells = <1>; 277 ti,mbox-num-users = <4>; 278 ti,mbox-num-fifos = <16>; 279 interrupt-parent = <&main_navss_intr>; 280 }; 281 282 mailbox0_cluster11: mailbox@31f8b000 { 283 compatible = "ti,am654-mailbox"; 284 reg = <0x00 0x31f8b000 0x00 0x200>; 285 #mbox-cells = <1>; 286 ti,mbox-num-users = <4>; 287 ti,mbox-num-fifos = <16>; 288 interrupt-parent = <&main_navss_intr>; 289 }; 290 291 main_ringacc: ringacc@3c000000 { 292 compatible = "ti,am654-navss-ringacc"; 293 reg = <0x0 0x3c000000 0x0 0x400000>, 294 <0x0 0x38000000 0x0 0x400000>, 295 <0x0 0x31120000 0x0 0x100>, 296 <0x0 0x33000000 0x0 0x40000>; 297 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 298 ti,num-rings = <1024>; 299 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 300 ti,sci = <&dmsc>; 301 ti,sci-dev-id = <211>; 302 msi-parent = <&main_udmass_inta>; 303 }; 304 305 main_udmap: dma-controller@31150000 { 306 compatible = "ti,j721e-navss-main-udmap"; 307 reg = <0x0 0x31150000 0x0 0x100>, 308 <0x0 0x34000000 0x0 0x100000>, 309 <0x0 0x35000000 0x0 0x100000>; 310 reg-names = "gcfg", "rchanrt", "tchanrt"; 311 msi-parent = <&main_udmass_inta>; 312 #dma-cells = <1>; 313 314 ti,sci = <&dmsc>; 315 ti,sci-dev-id = <212>; 316 ti,ringacc = <&main_ringacc>; 317 318 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 319 <0x0f>, /* TX_HCHAN */ 320 <0x10>; /* TX_UHCHAN */ 321 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 322 <0x0b>, /* RX_HCHAN */ 323 <0x0c>; /* RX_UHCHAN */ 324 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 325 }; 326 327 cpts@310d0000 { 328 compatible = "ti,j721e-cpts"; 329 reg = <0x0 0x310d0000 0x0 0x400>; 330 reg-names = "cpts"; 331 clocks = <&k3_clks 201 1>; 332 clock-names = "cpts"; 333 interrupts-extended = <&main_navss_intr 391>; 334 interrupt-names = "cpts"; 335 ti,cpts-periodic-outputs = <6>; 336 ti,cpts-ext-ts-inputs = <8>; 337 }; 338 }; 339 340 main_crypto: crypto@4e00000 { 341 compatible = "ti,j721e-sa2ul"; 342 reg = <0x0 0x4e00000 0x0 0x1200>; 343 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 344 #address-cells = <2>; 345 #size-cells = <2>; 346 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 347 348 status = "okay"; 349 350 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 351 <&main_udmap 0x4001>; 352 dma-names = "tx", "rx1", "rx2"; 353 dma-coherent; 354 355 rng: rng@4e10000 { 356 compatible = "inside-secure,safexcel-eip76"; 357 reg = <0x0 0x4e10000 0x0 0x7d>; 358 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 264 1>; 360 }; 361 }; 362 363 main_pmx0: pinctrl@11c000 { 364 compatible = "pinctrl-single"; 365 /* Proxy 0 addressing */ 366 reg = <0x0 0x11c000 0x0 0x2b4>; 367 #pinctrl-cells = <1>; 368 pinctrl-single,register-width = <32>; 369 pinctrl-single,function-mask = <0xffffffff>; 370 }; 371 372 dummy_cmn_refclk: dummy-cmn-refclk { 373 #clock-cells = <0>; 374 compatible = "fixed-clock"; 375 clock-frequency = <100000000>; 376 }; 377 378 dummy_cmn_refclk1: dummy-cmn-refclk1 { 379 #clock-cells = <0>; 380 compatible = "fixed-clock"; 381 clock-frequency = <100000000>; 382 }; 383 384 serdes_wiz0: wiz@5000000 { 385 compatible = "ti,j721e-wiz-16g"; 386 #address-cells = <1>; 387 #size-cells = <1>; 388 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 389 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 390 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 391 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 392 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 393 num-lanes = <2>; 394 #reset-cells = <1>; 395 ranges = <0x5000000 0x0 0x5000000 0x10000>; 396 397 wiz0_pll0_refclk: pll0-refclk { 398 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; 399 #clock-cells = <0>; 400 assigned-clocks = <&wiz0_pll0_refclk>; 401 assigned-clock-parents = <&k3_clks 292 11>; 402 }; 403 404 wiz0_pll1_refclk: pll1-refclk { 405 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; 406 #clock-cells = <0>; 407 assigned-clocks = <&wiz0_pll1_refclk>; 408 assigned-clock-parents = <&k3_clks 292 0>; 409 }; 410 411 wiz0_refclk_dig: refclk-dig { 412 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 413 #clock-cells = <0>; 414 assigned-clocks = <&wiz0_refclk_dig>; 415 assigned-clock-parents = <&k3_clks 292 11>; 416 }; 417 418 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 419 clocks = <&wiz0_refclk_dig>; 420 #clock-cells = <0>; 421 }; 422 423 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 424 clocks = <&wiz0_pll1_refclk>; 425 #clock-cells = <0>; 426 }; 427 428 serdes0: serdes@5000000 { 429 compatible = "ti,sierra-phy-t0"; 430 reg-names = "serdes"; 431 reg = <0x5000000 0x10000>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 resets = <&serdes_wiz0 0>; 435 reset-names = "sierra_reset"; 436 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 437 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 438 }; 439 }; 440 441 serdes_wiz1: wiz@5010000 { 442 compatible = "ti,j721e-wiz-16g"; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; 447 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 448 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 449 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 450 num-lanes = <2>; 451 #reset-cells = <1>; 452 ranges = <0x5010000 0x0 0x5010000 0x10000>; 453 454 wiz1_pll0_refclk: pll0-refclk { 455 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 456 #clock-cells = <0>; 457 assigned-clocks = <&wiz1_pll0_refclk>; 458 assigned-clock-parents = <&k3_clks 293 13>; 459 }; 460 461 wiz1_pll1_refclk: pll1-refclk { 462 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 463 #clock-cells = <0>; 464 assigned-clocks = <&wiz1_pll1_refclk>; 465 assigned-clock-parents = <&k3_clks 293 0>; 466 }; 467 468 wiz1_refclk_dig: refclk-dig { 469 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 470 #clock-cells = <0>; 471 assigned-clocks = <&wiz1_refclk_dig>; 472 assigned-clock-parents = <&k3_clks 293 13>; 473 }; 474 475 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 476 clocks = <&wiz1_refclk_dig>; 477 #clock-cells = <0>; 478 }; 479 480 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 481 clocks = <&wiz1_pll1_refclk>; 482 #clock-cells = <0>; 483 }; 484 485 serdes1: serdes@5010000 { 486 compatible = "ti,sierra-phy-t0"; 487 reg-names = "serdes"; 488 reg = <0x5010000 0x10000>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 resets = <&serdes_wiz1 0>; 492 reset-names = "sierra_reset"; 493 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 494 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 495 }; 496 }; 497 498 serdes_wiz2: wiz@5020000 { 499 compatible = "ti,j721e-wiz-16g"; 500 #address-cells = <1>; 501 #size-cells = <1>; 502 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 503 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; 504 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 505 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 506 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 507 num-lanes = <2>; 508 #reset-cells = <1>; 509 ranges = <0x5020000 0x0 0x5020000 0x10000>; 510 511 wiz2_pll0_refclk: pll0-refclk { 512 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; 513 #clock-cells = <0>; 514 assigned-clocks = <&wiz2_pll0_refclk>; 515 assigned-clock-parents = <&k3_clks 294 11>; 516 }; 517 518 wiz2_pll1_refclk: pll1-refclk { 519 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; 520 #clock-cells = <0>; 521 assigned-clocks = <&wiz2_pll1_refclk>; 522 assigned-clock-parents = <&k3_clks 294 0>; 523 }; 524 525 wiz2_refclk_dig: refclk-dig { 526 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 527 #clock-cells = <0>; 528 assigned-clocks = <&wiz2_refclk_dig>; 529 assigned-clock-parents = <&k3_clks 294 11>; 530 }; 531 532 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 533 clocks = <&wiz2_refclk_dig>; 534 #clock-cells = <0>; 535 }; 536 537 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 538 clocks = <&wiz2_pll1_refclk>; 539 #clock-cells = <0>; 540 }; 541 542 serdes2: serdes@5020000 { 543 compatible = "ti,sierra-phy-t0"; 544 reg-names = "serdes"; 545 reg = <0x5020000 0x10000>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 resets = <&serdes_wiz2 0>; 549 reset-names = "sierra_reset"; 550 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 551 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 552 }; 553 }; 554 555 serdes_wiz3: wiz@5030000 { 556 compatible = "ti,j721e-wiz-16g"; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 560 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; 561 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 562 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 563 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 564 num-lanes = <2>; 565 #reset-cells = <1>; 566 ranges = <0x5030000 0x0 0x5030000 0x10000>; 567 568 wiz3_pll0_refclk: pll0-refclk { 569 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; 570 #clock-cells = <0>; 571 assigned-clocks = <&wiz3_pll0_refclk>; 572 assigned-clock-parents = <&k3_clks 295 9>; 573 }; 574 575 wiz3_pll1_refclk: pll1-refclk { 576 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; 577 #clock-cells = <0>; 578 assigned-clocks = <&wiz3_pll1_refclk>; 579 assigned-clock-parents = <&k3_clks 295 0>; 580 }; 581 582 wiz3_refclk_dig: refclk-dig { 583 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 584 #clock-cells = <0>; 585 assigned-clocks = <&wiz3_refclk_dig>; 586 assigned-clock-parents = <&k3_clks 295 9>; 587 }; 588 589 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 590 clocks = <&wiz3_refclk_dig>; 591 #clock-cells = <0>; 592 }; 593 594 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 595 clocks = <&wiz3_pll1_refclk>; 596 #clock-cells = <0>; 597 }; 598 599 serdes3: serdes@5030000 { 600 compatible = "ti,sierra-phy-t0"; 601 reg-names = "serdes"; 602 reg = <0x5030000 0x10000>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 resets = <&serdes_wiz3 0>; 606 reset-names = "sierra_reset"; 607 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 608 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 609 }; 610 }; 611 612 pcie0_rc: pcie@2900000 { 613 compatible = "ti,j721e-pcie-host"; 614 reg = <0x00 0x02900000 0x00 0x1000>, 615 <0x00 0x02907000 0x00 0x400>, 616 <0x00 0x0d000000 0x00 0x00800000>, 617 <0x00 0x10000000 0x00 0x00001000>; 618 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 619 interrupt-names = "link_state"; 620 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 621 device_type = "pci"; 622 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 623 max-link-speed = <3>; 624 num-lanes = <2>; 625 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 626 clocks = <&k3_clks 239 1>; 627 clock-names = "fck"; 628 #address-cells = <3>; 629 #size-cells = <2>; 630 bus-range = <0x0 0xf>; 631 vendor-id = <0x104c>; 632 device-id = <0xb00d>; 633 msi-map = <0x0 &gic_its 0x0 0x10000>; 634 dma-coherent; 635 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 636 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 637 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 638 }; 639 640 pcie0_ep: pcie-ep@2900000 { 641 compatible = "ti,j721e-pcie-ep"; 642 reg = <0x00 0x02900000 0x00 0x1000>, 643 <0x00 0x02907000 0x00 0x400>, 644 <0x00 0x0d000000 0x00 0x00800000>, 645 <0x00 0x10000000 0x00 0x08000000>; 646 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 647 interrupt-names = "link_state"; 648 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 649 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 650 max-link-speed = <3>; 651 num-lanes = <2>; 652 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 653 clocks = <&k3_clks 239 1>; 654 clock-names = "fck"; 655 cdns,max-outbound-regions = <16>; 656 max-functions = /bits/ 8 <6>; 657 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 658 dma-coherent; 659 }; 660 661 pcie1_rc: pcie@2910000 { 662 compatible = "ti,j721e-pcie-host"; 663 reg = <0x00 0x02910000 0x00 0x1000>, 664 <0x00 0x02917000 0x00 0x400>, 665 <0x00 0x0d800000 0x00 0x00800000>, 666 <0x00 0x18000000 0x00 0x00001000>; 667 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 668 interrupt-names = "link_state"; 669 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 670 device_type = "pci"; 671 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 672 max-link-speed = <3>; 673 num-lanes = <2>; 674 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 675 clocks = <&k3_clks 240 1>; 676 clock-names = "fck"; 677 #address-cells = <3>; 678 #size-cells = <2>; 679 bus-range = <0x0 0xf>; 680 vendor-id = <0x104c>; 681 device-id = <0xb00d>; 682 msi-map = <0x0 &gic_its 0x10000 0x10000>; 683 dma-coherent; 684 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 685 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 686 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 687 }; 688 689 pcie1_ep: pcie-ep@2910000 { 690 compatible = "ti,j721e-pcie-ep"; 691 reg = <0x00 0x02910000 0x00 0x1000>, 692 <0x00 0x02917000 0x00 0x400>, 693 <0x00 0x0d800000 0x00 0x00800000>, 694 <0x00 0x18000000 0x00 0x08000000>; 695 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 696 interrupt-names = "link_state"; 697 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 698 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 699 max-link-speed = <3>; 700 num-lanes = <2>; 701 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 702 clocks = <&k3_clks 240 1>; 703 clock-names = "fck"; 704 cdns,max-outbound-regions = <16>; 705 max-functions = /bits/ 8 <6>; 706 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 707 dma-coherent; 708 }; 709 710 pcie2_rc: pcie@2920000 { 711 compatible = "ti,j721e-pcie-host"; 712 reg = <0x00 0x02920000 0x00 0x1000>, 713 <0x00 0x02927000 0x00 0x400>, 714 <0x00 0x0e000000 0x00 0x00800000>, 715 <0x44 0x00000000 0x00 0x00001000>; 716 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 717 interrupt-names = "link_state"; 718 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 719 device_type = "pci"; 720 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 721 max-link-speed = <3>; 722 num-lanes = <2>; 723 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 724 clocks = <&k3_clks 241 1>; 725 clock-names = "fck"; 726 #address-cells = <3>; 727 #size-cells = <2>; 728 bus-range = <0x0 0xf>; 729 vendor-id = <0x104c>; 730 device-id = <0xb00d>; 731 msi-map = <0x0 &gic_its 0x20000 0x10000>; 732 dma-coherent; 733 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 734 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 735 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 736 }; 737 738 pcie2_ep: pcie-ep@2920000 { 739 compatible = "ti,j721e-pcie-ep"; 740 reg = <0x00 0x02920000 0x00 0x1000>, 741 <0x00 0x02927000 0x00 0x400>, 742 <0x00 0x0e000000 0x00 0x00800000>, 743 <0x44 0x00000000 0x00 0x08000000>; 744 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 745 interrupt-names = "link_state"; 746 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 747 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 748 max-link-speed = <3>; 749 num-lanes = <2>; 750 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 751 clocks = <&k3_clks 241 1>; 752 clock-names = "fck"; 753 cdns,max-outbound-regions = <16>; 754 max-functions = /bits/ 8 <6>; 755 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 756 dma-coherent; 757 }; 758 759 pcie3_rc: pcie@2930000 { 760 compatible = "ti,j721e-pcie-host"; 761 reg = <0x00 0x02930000 0x00 0x1000>, 762 <0x00 0x02937000 0x00 0x400>, 763 <0x00 0x0e800000 0x00 0x00800000>, 764 <0x44 0x10000000 0x00 0x00001000>; 765 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 766 interrupt-names = "link_state"; 767 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 768 device_type = "pci"; 769 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 770 max-link-speed = <3>; 771 num-lanes = <2>; 772 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 773 clocks = <&k3_clks 242 1>; 774 clock-names = "fck"; 775 #address-cells = <3>; 776 #size-cells = <2>; 777 bus-range = <0x0 0xf>; 778 vendor-id = <0x104c>; 779 device-id = <0xb00d>; 780 msi-map = <0x0 &gic_its 0x30000 0x10000>; 781 dma-coherent; 782 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 783 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 784 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 785 }; 786 787 pcie3_ep: pcie-ep@2930000 { 788 compatible = "ti,j721e-pcie-ep"; 789 reg = <0x00 0x02930000 0x00 0x1000>, 790 <0x00 0x02937000 0x00 0x400>, 791 <0x00 0x0e800000 0x00 0x00800000>, 792 <0x44 0x10000000 0x00 0x08000000>; 793 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 794 interrupt-names = "link_state"; 795 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 796 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 797 max-link-speed = <3>; 798 num-lanes = <2>; 799 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 800 clocks = <&k3_clks 242 1>; 801 clock-names = "fck"; 802 cdns,max-outbound-regions = <16>; 803 max-functions = /bits/ 8 <6>; 804 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 805 dma-coherent; 806 #address-cells = <2>; 807 #size-cells = <2>; 808 }; 809 810 main_uart0: serial@2800000 { 811 compatible = "ti,j721e-uart", "ti,am654-uart"; 812 reg = <0x00 0x02800000 0x00 0x100>; 813 reg-shift = <2>; 814 reg-io-width = <4>; 815 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 816 clock-frequency = <48000000>; 817 current-speed = <115200>; 818 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 819 clocks = <&k3_clks 146 0>; 820 clock-names = "fclk"; 821 }; 822 823 main_uart1: serial@2810000 { 824 compatible = "ti,j721e-uart", "ti,am654-uart"; 825 reg = <0x00 0x02810000 0x00 0x100>; 826 reg-shift = <2>; 827 reg-io-width = <4>; 828 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 829 clock-frequency = <48000000>; 830 current-speed = <115200>; 831 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 832 clocks = <&k3_clks 278 0>; 833 clock-names = "fclk"; 834 }; 835 836 main_uart2: serial@2820000 { 837 compatible = "ti,j721e-uart", "ti,am654-uart"; 838 reg = <0x00 0x02820000 0x00 0x100>; 839 reg-shift = <2>; 840 reg-io-width = <4>; 841 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 842 clock-frequency = <48000000>; 843 current-speed = <115200>; 844 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 845 clocks = <&k3_clks 279 0>; 846 clock-names = "fclk"; 847 }; 848 849 main_uart3: serial@2830000 { 850 compatible = "ti,j721e-uart", "ti,am654-uart"; 851 reg = <0x00 0x02830000 0x00 0x100>; 852 reg-shift = <2>; 853 reg-io-width = <4>; 854 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 855 clock-frequency = <48000000>; 856 current-speed = <115200>; 857 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 858 clocks = <&k3_clks 280 0>; 859 clock-names = "fclk"; 860 }; 861 862 main_uart4: serial@2840000 { 863 compatible = "ti,j721e-uart", "ti,am654-uart"; 864 reg = <0x00 0x02840000 0x00 0x100>; 865 reg-shift = <2>; 866 reg-io-width = <4>; 867 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 868 clock-frequency = <48000000>; 869 current-speed = <115200>; 870 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 871 clocks = <&k3_clks 281 0>; 872 clock-names = "fclk"; 873 }; 874 875 main_uart5: serial@2850000 { 876 compatible = "ti,j721e-uart", "ti,am654-uart"; 877 reg = <0x00 0x02850000 0x00 0x100>; 878 reg-shift = <2>; 879 reg-io-width = <4>; 880 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 881 clock-frequency = <48000000>; 882 current-speed = <115200>; 883 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&k3_clks 282 0>; 885 clock-names = "fclk"; 886 }; 887 888 main_uart6: serial@2860000 { 889 compatible = "ti,j721e-uart", "ti,am654-uart"; 890 reg = <0x00 0x02860000 0x00 0x100>; 891 reg-shift = <2>; 892 reg-io-width = <4>; 893 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 894 clock-frequency = <48000000>; 895 current-speed = <115200>; 896 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 897 clocks = <&k3_clks 283 0>; 898 clock-names = "fclk"; 899 }; 900 901 main_uart7: serial@2870000 { 902 compatible = "ti,j721e-uart", "ti,am654-uart"; 903 reg = <0x00 0x02870000 0x00 0x100>; 904 reg-shift = <2>; 905 reg-io-width = <4>; 906 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 907 clock-frequency = <48000000>; 908 current-speed = <115200>; 909 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&k3_clks 284 0>; 911 clock-names = "fclk"; 912 }; 913 914 main_uart8: serial@2880000 { 915 compatible = "ti,j721e-uart", "ti,am654-uart"; 916 reg = <0x00 0x02880000 0x00 0x100>; 917 reg-shift = <2>; 918 reg-io-width = <4>; 919 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 920 clock-frequency = <48000000>; 921 current-speed = <115200>; 922 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 923 clocks = <&k3_clks 285 0>; 924 clock-names = "fclk"; 925 }; 926 927 main_uart9: serial@2890000 { 928 compatible = "ti,j721e-uart", "ti,am654-uart"; 929 reg = <0x00 0x02890000 0x00 0x100>; 930 reg-shift = <2>; 931 reg-io-width = <4>; 932 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 933 clock-frequency = <48000000>; 934 current-speed = <115200>; 935 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 936 clocks = <&k3_clks 286 0>; 937 clock-names = "fclk"; 938 }; 939 940 main_gpio0: gpio@600000 { 941 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 942 reg = <0x0 0x00600000 0x0 0x100>; 943 gpio-controller; 944 #gpio-cells = <2>; 945 interrupt-parent = <&main_gpio_intr>; 946 interrupts = <256>, <257>, <258>, <259>, 947 <260>, <261>, <262>, <263>; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 ti,ngpio = <128>; 951 ti,davinci-gpio-unbanked = <0>; 952 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 953 clocks = <&k3_clks 105 0>; 954 clock-names = "gpio"; 955 }; 956 957 main_gpio1: gpio@601000 { 958 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 959 reg = <0x0 0x00601000 0x0 0x100>; 960 gpio-controller; 961 #gpio-cells = <2>; 962 interrupt-parent = <&main_gpio_intr>; 963 interrupts = <288>, <289>, <290>; 964 interrupt-controller; 965 #interrupt-cells = <2>; 966 ti,ngpio = <36>; 967 ti,davinci-gpio-unbanked = <0>; 968 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 969 clocks = <&k3_clks 106 0>; 970 clock-names = "gpio"; 971 }; 972 973 main_gpio2: gpio@610000 { 974 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 975 reg = <0x0 0x00610000 0x0 0x100>; 976 gpio-controller; 977 #gpio-cells = <2>; 978 interrupt-parent = <&main_gpio_intr>; 979 interrupts = <264>, <265>, <266>, <267>, 980 <268>, <269>, <270>, <271>; 981 interrupt-controller; 982 #interrupt-cells = <2>; 983 ti,ngpio = <128>; 984 ti,davinci-gpio-unbanked = <0>; 985 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 986 clocks = <&k3_clks 107 0>; 987 clock-names = "gpio"; 988 }; 989 990 main_gpio3: gpio@611000 { 991 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 992 reg = <0x0 0x00611000 0x0 0x100>; 993 gpio-controller; 994 #gpio-cells = <2>; 995 interrupt-parent = <&main_gpio_intr>; 996 interrupts = <292>, <293>, <294>; 997 interrupt-controller; 998 #interrupt-cells = <2>; 999 ti,ngpio = <36>; 1000 ti,davinci-gpio-unbanked = <0>; 1001 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1002 clocks = <&k3_clks 108 0>; 1003 clock-names = "gpio"; 1004 }; 1005 1006 main_gpio4: gpio@620000 { 1007 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1008 reg = <0x0 0x00620000 0x0 0x100>; 1009 gpio-controller; 1010 #gpio-cells = <2>; 1011 interrupt-parent = <&main_gpio_intr>; 1012 interrupts = <272>, <273>, <274>, <275>, 1013 <276>, <277>, <278>, <279>; 1014 interrupt-controller; 1015 #interrupt-cells = <2>; 1016 ti,ngpio = <128>; 1017 ti,davinci-gpio-unbanked = <0>; 1018 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1019 clocks = <&k3_clks 109 0>; 1020 clock-names = "gpio"; 1021 }; 1022 1023 main_gpio5: gpio@621000 { 1024 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1025 reg = <0x0 0x00621000 0x0 0x100>; 1026 gpio-controller; 1027 #gpio-cells = <2>; 1028 interrupt-parent = <&main_gpio_intr>; 1029 interrupts = <296>, <297>, <298>; 1030 interrupt-controller; 1031 #interrupt-cells = <2>; 1032 ti,ngpio = <36>; 1033 ti,davinci-gpio-unbanked = <0>; 1034 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1035 clocks = <&k3_clks 110 0>; 1036 clock-names = "gpio"; 1037 }; 1038 1039 main_gpio6: gpio@630000 { 1040 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1041 reg = <0x0 0x00630000 0x0 0x100>; 1042 gpio-controller; 1043 #gpio-cells = <2>; 1044 interrupt-parent = <&main_gpio_intr>; 1045 interrupts = <280>, <281>, <282>, <283>, 1046 <284>, <285>, <286>, <287>; 1047 interrupt-controller; 1048 #interrupt-cells = <2>; 1049 ti,ngpio = <128>; 1050 ti,davinci-gpio-unbanked = <0>; 1051 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1052 clocks = <&k3_clks 111 0>; 1053 clock-names = "gpio"; 1054 }; 1055 1056 main_gpio7: gpio@631000 { 1057 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1058 reg = <0x0 0x00631000 0x0 0x100>; 1059 gpio-controller; 1060 #gpio-cells = <2>; 1061 interrupt-parent = <&main_gpio_intr>; 1062 interrupts = <300>, <301>, <302>; 1063 interrupt-controller; 1064 #interrupt-cells = <2>; 1065 ti,ngpio = <36>; 1066 ti,davinci-gpio-unbanked = <0>; 1067 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1068 clocks = <&k3_clks 112 0>; 1069 clock-names = "gpio"; 1070 }; 1071 1072 main_sdhci0: sdhci@4f80000 { 1073 compatible = "ti,j721e-sdhci-8bit"; 1074 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1075 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1077 clock-names = "clk_xin", "clk_ahb"; 1078 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 1079 assigned-clocks = <&k3_clks 91 1>; 1080 assigned-clock-parents = <&k3_clks 91 2>; 1081 bus-width = <8>; 1082 mmc-hs400-1_8v; 1083 mmc-ddr-1_8v; 1084 ti,otap-del-sel = <0x2>; 1085 ti,trm-icp = <0x8>; 1086 ti,strobe-sel = <0x77>; 1087 dma-coherent; 1088 }; 1089 1090 main_sdhci1: sdhci@4fb0000 { 1091 compatible = "ti,j721e-sdhci-4bit"; 1092 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1093 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1094 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1095 clock-names = "clk_xin", "clk_ahb"; 1096 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 1097 assigned-clocks = <&k3_clks 92 0>; 1098 assigned-clock-parents = <&k3_clks 92 1>; 1099 ti,otap-del-sel = <0x2>; 1100 ti,trm-icp = <0x8>; 1101 ti,clkbuf-sel = <0x7>; 1102 dma-coherent; 1103 no-1-8-v; 1104 }; 1105 1106 main_sdhci2: sdhci@4f98000 { 1107 compatible = "ti,j721e-sdhci-4bit"; 1108 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1109 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1110 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1111 clock-names = "clk_xin", "clk_ahb"; 1112 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 1113 assigned-clocks = <&k3_clks 93 0>; 1114 assigned-clock-parents = <&k3_clks 93 1>; 1115 ti,otap-del-sel = <0x2>; 1116 ti,trm-icp = <0x8>; 1117 ti,clkbuf-sel = <0x7>; 1118 dma-coherent; 1119 no-1-8-v; 1120 }; 1121 1122 usbss0: cdns-usb@4104000 { 1123 compatible = "ti,j721e-usb"; 1124 reg = <0x00 0x4104000 0x00 0x100>; 1125 dma-coherent; 1126 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1127 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1128 clock-names = "ref", "lpm"; 1129 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1130 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1131 #address-cells = <2>; 1132 #size-cells = <2>; 1133 ranges; 1134 1135 usb0: usb@6000000 { 1136 compatible = "cdns,usb3"; 1137 reg = <0x00 0x6000000 0x00 0x10000>, 1138 <0x00 0x6010000 0x00 0x10000>, 1139 <0x00 0x6020000 0x00 0x10000>; 1140 reg-names = "otg", "xhci", "dev"; 1141 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1142 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1143 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1144 interrupt-names = "host", 1145 "peripheral", 1146 "otg"; 1147 maximum-speed = "super-speed"; 1148 dr_mode = "otg"; 1149 }; 1150 }; 1151 1152 usbss1: cdns-usb@4114000 { 1153 compatible = "ti,j721e-usb"; 1154 reg = <0x00 0x4114000 0x00 0x100>; 1155 dma-coherent; 1156 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1157 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1158 clock-names = "ref", "lpm"; 1159 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1160 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1161 #address-cells = <2>; 1162 #size-cells = <2>; 1163 ranges; 1164 1165 usb1: usb@6400000 { 1166 compatible = "cdns,usb3"; 1167 reg = <0x00 0x6400000 0x00 0x10000>, 1168 <0x00 0x6410000 0x00 0x10000>, 1169 <0x00 0x6420000 0x00 0x10000>; 1170 reg-names = "otg", "xhci", "dev"; 1171 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1172 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1173 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1174 interrupt-names = "host", 1175 "peripheral", 1176 "otg"; 1177 maximum-speed = "super-speed"; 1178 dr_mode = "otg"; 1179 }; 1180 }; 1181 1182 main_i2c0: i2c@2000000 { 1183 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1184 reg = <0x0 0x2000000 0x0 0x100>; 1185 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 clock-names = "fck"; 1189 clocks = <&k3_clks 187 0>; 1190 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1191 }; 1192 1193 main_i2c1: i2c@2010000 { 1194 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1195 reg = <0x0 0x2010000 0x0 0x100>; 1196 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clock-names = "fck"; 1200 clocks = <&k3_clks 188 0>; 1201 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1202 }; 1203 1204 main_i2c2: i2c@2020000 { 1205 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1206 reg = <0x0 0x2020000 0x0 0x100>; 1207 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 clock-names = "fck"; 1211 clocks = <&k3_clks 189 0>; 1212 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1213 }; 1214 1215 main_i2c3: i2c@2030000 { 1216 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1217 reg = <0x0 0x2030000 0x0 0x100>; 1218 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 clock-names = "fck"; 1222 clocks = <&k3_clks 190 0>; 1223 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1224 }; 1225 1226 main_i2c4: i2c@2040000 { 1227 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1228 reg = <0x0 0x2040000 0x0 0x100>; 1229 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clock-names = "fck"; 1233 clocks = <&k3_clks 191 0>; 1234 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1235 }; 1236 1237 main_i2c5: i2c@2050000 { 1238 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1239 reg = <0x0 0x2050000 0x0 0x100>; 1240 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 clock-names = "fck"; 1244 clocks = <&k3_clks 192 0>; 1245 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1246 }; 1247 1248 main_i2c6: i2c@2060000 { 1249 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1250 reg = <0x0 0x2060000 0x0 0x100>; 1251 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 clock-names = "fck"; 1255 clocks = <&k3_clks 193 0>; 1256 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1257 }; 1258 1259 ufs_wrapper: ufs-wrapper@4e80000 { 1260 compatible = "ti,j721e-ufs"; 1261 reg = <0x0 0x4e80000 0x0 0x100>; 1262 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1263 clocks = <&k3_clks 277 1>; 1264 assigned-clocks = <&k3_clks 277 1>; 1265 assigned-clock-parents = <&k3_clks 277 4>; 1266 ranges; 1267 #address-cells = <2>; 1268 #size-cells = <2>; 1269 1270 ufs@4e84000 { 1271 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1272 reg = <0x0 0x4e84000 0x0 0x10000>; 1273 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1274 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1275 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1276 clock-names = "core_clk", "phy_clk", "ref_clk"; 1277 dma-coherent; 1278 }; 1279 }; 1280 1281 dss: dss@04a00000 { 1282 compatible = "ti,j721e-dss"; 1283 reg = 1284 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1285 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1286 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1287 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1288 1289 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1290 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1291 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1292 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1293 1294 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1295 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1296 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1297 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1298 1299 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1300 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1301 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1302 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1303 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1304 1305 reg-names = "common_m", "common_s0", 1306 "common_s1", "common_s2", 1307 "vidl1", "vidl2","vid1","vid2", 1308 "ovr1", "ovr2", "ovr3", "ovr4", 1309 "vp1", "vp2", "vp3", "vp4", 1310 "wb"; 1311 1312 clocks = <&k3_clks 152 0>, 1313 <&k3_clks 152 1>, 1314 <&k3_clks 152 4>, 1315 <&k3_clks 152 9>, 1316 <&k3_clks 152 13>; 1317 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1318 1319 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1320 1321 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "common_m", 1326 "common_s0", 1327 "common_s1", 1328 "common_s2"; 1329 1330 status = "disabled"; 1331 1332 dss_ports: ports { 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 }; 1336 }; 1337 1338 mcasp0: mcasp@2b00000 { 1339 compatible = "ti,am33xx-mcasp-audio"; 1340 reg = <0x0 0x02b00000 0x0 0x2000>, 1341 <0x0 0x02b08000 0x0 0x1000>; 1342 reg-names = "mpu","dat"; 1343 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1345 interrupt-names = "tx", "rx"; 1346 1347 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1348 dma-names = "tx", "rx"; 1349 1350 clocks = <&k3_clks 174 1>; 1351 clock-names = "fck"; 1352 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1353 1354 status = "disabled"; 1355 }; 1356 1357 mcasp1: mcasp@2b10000 { 1358 compatible = "ti,am33xx-mcasp-audio"; 1359 reg = <0x0 0x02b10000 0x0 0x2000>, 1360 <0x0 0x02b18000 0x0 0x1000>; 1361 reg-names = "mpu","dat"; 1362 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "tx", "rx"; 1365 1366 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1367 dma-names = "tx", "rx"; 1368 1369 clocks = <&k3_clks 175 1>; 1370 clock-names = "fck"; 1371 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1372 1373 status = "disabled"; 1374 }; 1375 1376 mcasp2: mcasp@2b20000 { 1377 compatible = "ti,am33xx-mcasp-audio"; 1378 reg = <0x0 0x02b20000 0x0 0x2000>, 1379 <0x0 0x02b28000 0x0 0x1000>; 1380 reg-names = "mpu","dat"; 1381 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1383 interrupt-names = "tx", "rx"; 1384 1385 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1386 dma-names = "tx", "rx"; 1387 1388 clocks = <&k3_clks 176 1>; 1389 clock-names = "fck"; 1390 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1391 1392 status = "disabled"; 1393 }; 1394 1395 mcasp3: mcasp@2b30000 { 1396 compatible = "ti,am33xx-mcasp-audio"; 1397 reg = <0x0 0x02b30000 0x0 0x2000>, 1398 <0x0 0x02b38000 0x0 0x1000>; 1399 reg-names = "mpu","dat"; 1400 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1402 interrupt-names = "tx", "rx"; 1403 1404 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1405 dma-names = "tx", "rx"; 1406 1407 clocks = <&k3_clks 177 1>; 1408 clock-names = "fck"; 1409 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1410 1411 status = "disabled"; 1412 }; 1413 1414 mcasp4: mcasp@2b40000 { 1415 compatible = "ti,am33xx-mcasp-audio"; 1416 reg = <0x0 0x02b40000 0x0 0x2000>, 1417 <0x0 0x02b48000 0x0 0x1000>; 1418 reg-names = "mpu","dat"; 1419 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1421 interrupt-names = "tx", "rx"; 1422 1423 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1424 dma-names = "tx", "rx"; 1425 1426 clocks = <&k3_clks 178 1>; 1427 clock-names = "fck"; 1428 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1429 1430 status = "disabled"; 1431 }; 1432 1433 mcasp5: mcasp@2b50000 { 1434 compatible = "ti,am33xx-mcasp-audio"; 1435 reg = <0x0 0x02b50000 0x0 0x2000>, 1436 <0x0 0x02b58000 0x0 0x1000>; 1437 reg-names = "mpu","dat"; 1438 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1440 interrupt-names = "tx", "rx"; 1441 1442 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1443 dma-names = "tx", "rx"; 1444 1445 clocks = <&k3_clks 179 1>; 1446 clock-names = "fck"; 1447 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1448 1449 status = "disabled"; 1450 }; 1451 1452 mcasp6: mcasp@2b60000 { 1453 compatible = "ti,am33xx-mcasp-audio"; 1454 reg = <0x0 0x02b60000 0x0 0x2000>, 1455 <0x0 0x02b68000 0x0 0x1000>; 1456 reg-names = "mpu","dat"; 1457 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1459 interrupt-names = "tx", "rx"; 1460 1461 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1462 dma-names = "tx", "rx"; 1463 1464 clocks = <&k3_clks 180 1>; 1465 clock-names = "fck"; 1466 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1467 1468 status = "disabled"; 1469 }; 1470 1471 mcasp7: mcasp@2b70000 { 1472 compatible = "ti,am33xx-mcasp-audio"; 1473 reg = <0x0 0x02b70000 0x0 0x2000>, 1474 <0x0 0x02b78000 0x0 0x1000>; 1475 reg-names = "mpu","dat"; 1476 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupt-names = "tx", "rx"; 1479 1480 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1481 dma-names = "tx", "rx"; 1482 1483 clocks = <&k3_clks 181 1>; 1484 clock-names = "fck"; 1485 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1486 1487 status = "disabled"; 1488 }; 1489 1490 mcasp8: mcasp@2b80000 { 1491 compatible = "ti,am33xx-mcasp-audio"; 1492 reg = <0x0 0x02b80000 0x0 0x2000>, 1493 <0x0 0x02b88000 0x0 0x1000>; 1494 reg-names = "mpu","dat"; 1495 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1497 interrupt-names = "tx", "rx"; 1498 1499 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1500 dma-names = "tx", "rx"; 1501 1502 clocks = <&k3_clks 182 1>; 1503 clock-names = "fck"; 1504 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1505 1506 status = "disabled"; 1507 }; 1508 1509 mcasp9: mcasp@2b90000 { 1510 compatible = "ti,am33xx-mcasp-audio"; 1511 reg = <0x0 0x02b90000 0x0 0x2000>, 1512 <0x0 0x02b98000 0x0 0x1000>; 1513 reg-names = "mpu","dat"; 1514 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1516 interrupt-names = "tx", "rx"; 1517 1518 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1519 dma-names = "tx", "rx"; 1520 1521 clocks = <&k3_clks 183 1>; 1522 clock-names = "fck"; 1523 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1524 1525 status = "disabled"; 1526 }; 1527 1528 mcasp10: mcasp@2ba0000 { 1529 compatible = "ti,am33xx-mcasp-audio"; 1530 reg = <0x0 0x02ba0000 0x0 0x2000>, 1531 <0x0 0x02ba8000 0x0 0x1000>; 1532 reg-names = "mpu","dat"; 1533 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1535 interrupt-names = "tx", "rx"; 1536 1537 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1538 dma-names = "tx", "rx"; 1539 1540 clocks = <&k3_clks 184 1>; 1541 clock-names = "fck"; 1542 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1543 1544 status = "disabled"; 1545 }; 1546 1547 mcasp11: mcasp@2bb0000 { 1548 compatible = "ti,am33xx-mcasp-audio"; 1549 reg = <0x0 0x02bb0000 0x0 0x2000>, 1550 <0x0 0x02bb8000 0x0 0x1000>; 1551 reg-names = "mpu","dat"; 1552 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1554 interrupt-names = "tx", "rx"; 1555 1556 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1557 dma-names = "tx", "rx"; 1558 1559 clocks = <&k3_clks 185 1>; 1560 clock-names = "fck"; 1561 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1562 1563 status = "disabled"; 1564 }; 1565 1566 watchdog0: watchdog@2200000 { 1567 compatible = "ti,j7-rti-wdt"; 1568 reg = <0x0 0x2200000 0x0 0x100>; 1569 clocks = <&k3_clks 252 1>; 1570 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1571 assigned-clocks = <&k3_clks 252 1>; 1572 assigned-clock-parents = <&k3_clks 252 5>; 1573 }; 1574 1575 watchdog1: watchdog@2210000 { 1576 compatible = "ti,j7-rti-wdt"; 1577 reg = <0x0 0x2210000 0x0 0x100>; 1578 clocks = <&k3_clks 253 1>; 1579 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1580 assigned-clocks = <&k3_clks 253 1>; 1581 assigned-clock-parents = <&k3_clks 253 5>; 1582 }; 1583 1584 c66_0: dsp@4d80800000 { 1585 compatible = "ti,j721e-c66-dsp"; 1586 reg = <0x4d 0x80800000 0x00 0x00048000>, 1587 <0x4d 0x80e00000 0x00 0x00008000>, 1588 <0x4d 0x80f00000 0x00 0x00008000>; 1589 reg-names = "l2sram", "l1pram", "l1dram"; 1590 ti,sci = <&dmsc>; 1591 ti,sci-dev-id = <142>; 1592 ti,sci-proc-ids = <0x03 0xff>; 1593 resets = <&k3_reset 142 1>; 1594 firmware-name = "j7-c66_0-fw"; 1595 }; 1596 1597 c66_1: dsp@4d81800000 { 1598 compatible = "ti,j721e-c66-dsp"; 1599 reg = <0x4d 0x81800000 0x00 0x00048000>, 1600 <0x4d 0x81e00000 0x00 0x00008000>, 1601 <0x4d 0x81f00000 0x00 0x00008000>; 1602 reg-names = "l2sram", "l1pram", "l1dram"; 1603 ti,sci = <&dmsc>; 1604 ti,sci-dev-id = <143>; 1605 ti,sci-proc-ids = <0x04 0xff>; 1606 resets = <&k3_reset 143 1>; 1607 firmware-name = "j7-c66_1-fw"; 1608 }; 1609 1610 c71_0: dsp@64800000 { 1611 compatible = "ti,j721e-c71-dsp"; 1612 reg = <0x00 0x64800000 0x00 0x00080000>, 1613 <0x00 0x64e00000 0x00 0x0000c000>; 1614 reg-names = "l2sram", "l1dram"; 1615 ti,sci = <&dmsc>; 1616 ti,sci-dev-id = <15>; 1617 ti,sci-proc-ids = <0x30 0xff>; 1618 resets = <&k3_reset 15 1>; 1619 firmware-name = "j7-c71_0-fw"; 1620 }; 1621}; 1622