1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/mux-j721e-wiz.h> 10 11&cbass_main { 12 msmc_ram: sram@70000000 { 13 compatible = "mmio-sram"; 14 reg = <0x0 0x70000000 0x0 0x800000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x0 0x0 0x70000000 0x800000>; 18 19 atf-sram@0 { 20 reg = <0x0 0x20000>; 21 }; 22 }; 23 24 scm_conf: scm-conf@100000 { 25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x0 0x0 0x00100000 0x1c000>; 30 31 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 32 compatible = "mmio-mux"; 33 reg = <0x00004080 0x50>; 34 #mux-control-cells = <1>; 35 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 36 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 37 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 38 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 39 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 40 /* SERDES4 lane0/1/2/3 select */ 41 idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, 42 <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, 43 <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, 44 <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>, 45 <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; 46 }; 47 48 usb_serdes_mux: mux-controller@4000 { 49 compatible = "mmio-mux"; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 52 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 65 66 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 67 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 68 69 gic_its: msi-controller@1820000 { 70 compatible = "arm,gic-v3-its"; 71 reg = <0x00 0x01820000 0x00 0x10000>; 72 socionext,synquacer-pre-its = <0x1000000 0x400000>; 73 msi-controller; 74 #msi-cells = <1>; 75 }; 76 }; 77 78 main_gpio_intr: interrupt-controller0 { 79 compatible = "ti,sci-intr"; 80 ti,intr-trigger-type = <1>; 81 interrupt-controller; 82 interrupt-parent = <&gic500>; 83 #interrupt-cells = <1>; 84 ti,sci = <&dmsc>; 85 ti,sci-dev-id = <131>; 86 ti,interrupt-ranges = <8 392 56>; 87 }; 88 89 main_navss { 90 compatible = "simple-mfd"; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 dma-coherent; 95 dma-ranges; 96 97 ti,sci-dev-id = <199>; 98 99 main_navss_intr: interrupt-controller1 { 100 compatible = "ti,sci-intr"; 101 ti,intr-trigger-type = <4>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 #interrupt-cells = <1>; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <213>; 107 ti,interrupt-ranges = <0 64 64>, 108 <64 448 64>, 109 <128 672 64>; 110 }; 111 112 main_udmass_inta: interrupt-controller@33d00000 { 113 compatible = "ti,sci-inta"; 114 reg = <0x0 0x33d00000 0x0 0x100000>; 115 interrupt-controller; 116 interrupt-parent = <&main_navss_intr>; 117 msi-controller; 118 ti,sci = <&dmsc>; 119 ti,sci-dev-id = <209>; 120 ti,interrupt-ranges = <0 0 256>; 121 }; 122 123 secure_proxy_main: mailbox@32c00000 { 124 compatible = "ti,am654-secure-proxy"; 125 #mbox-cells = <1>; 126 reg-names = "target_data", "rt", "scfg"; 127 reg = <0x00 0x32c00000 0x00 0x100000>, 128 <0x00 0x32400000 0x00 0x100000>, 129 <0x00 0x32800000 0x00 0x100000>; 130 interrupt-names = "rx_011"; 131 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 132 }; 133 134 smmu0: iommu@36600000 { 135 compatible = "arm,smmu-v3"; 136 reg = <0x0 0x36600000 0x0 0x100000>; 137 interrupt-parent = <&gic500>; 138 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 139 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 140 interrupt-names = "eventq", "gerror"; 141 #iommu-cells = <1>; 142 }; 143 144 hwspinlock: spinlock@30e00000 { 145 compatible = "ti,am654-hwspinlock"; 146 reg = <0x00 0x30e00000 0x00 0x1000>; 147 #hwlock-cells = <1>; 148 }; 149 150 mailbox0_cluster0: mailbox@31f80000 { 151 compatible = "ti,am654-mailbox"; 152 reg = <0x00 0x31f80000 0x00 0x200>; 153 #mbox-cells = <1>; 154 ti,mbox-num-users = <4>; 155 ti,mbox-num-fifos = <16>; 156 interrupt-parent = <&main_navss_intr>; 157 }; 158 159 mailbox0_cluster1: mailbox@31f81000 { 160 compatible = "ti,am654-mailbox"; 161 reg = <0x00 0x31f81000 0x00 0x200>; 162 #mbox-cells = <1>; 163 ti,mbox-num-users = <4>; 164 ti,mbox-num-fifos = <16>; 165 interrupt-parent = <&main_navss_intr>; 166 }; 167 168 mailbox0_cluster2: mailbox@31f82000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f82000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 }; 176 177 mailbox0_cluster3: mailbox@31f83000 { 178 compatible = "ti,am654-mailbox"; 179 reg = <0x00 0x31f83000 0x00 0x200>; 180 #mbox-cells = <1>; 181 ti,mbox-num-users = <4>; 182 ti,mbox-num-fifos = <16>; 183 interrupt-parent = <&main_navss_intr>; 184 }; 185 186 mailbox0_cluster4: mailbox@31f84000 { 187 compatible = "ti,am654-mailbox"; 188 reg = <0x00 0x31f84000 0x00 0x200>; 189 #mbox-cells = <1>; 190 ti,mbox-num-users = <4>; 191 ti,mbox-num-fifos = <16>; 192 interrupt-parent = <&main_navss_intr>; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 }; 203 204 mailbox0_cluster6: mailbox@31f86000 { 205 compatible = "ti,am654-mailbox"; 206 reg = <0x00 0x31f86000 0x00 0x200>; 207 #mbox-cells = <1>; 208 ti,mbox-num-users = <4>; 209 ti,mbox-num-fifos = <16>; 210 interrupt-parent = <&main_navss_intr>; 211 }; 212 213 mailbox0_cluster7: mailbox@31f87000 { 214 compatible = "ti,am654-mailbox"; 215 reg = <0x00 0x31f87000 0x00 0x200>; 216 #mbox-cells = <1>; 217 ti,mbox-num-users = <4>; 218 ti,mbox-num-fifos = <16>; 219 interrupt-parent = <&main_navss_intr>; 220 }; 221 222 mailbox0_cluster8: mailbox@31f88000 { 223 compatible = "ti,am654-mailbox"; 224 reg = <0x00 0x31f88000 0x00 0x200>; 225 #mbox-cells = <1>; 226 ti,mbox-num-users = <4>; 227 ti,mbox-num-fifos = <16>; 228 interrupt-parent = <&main_navss_intr>; 229 }; 230 231 mailbox0_cluster9: mailbox@31f89000 { 232 compatible = "ti,am654-mailbox"; 233 reg = <0x00 0x31f89000 0x00 0x200>; 234 #mbox-cells = <1>; 235 ti,mbox-num-users = <4>; 236 ti,mbox-num-fifos = <16>; 237 interrupt-parent = <&main_navss_intr>; 238 }; 239 240 mailbox0_cluster10: mailbox@31f8a000 { 241 compatible = "ti,am654-mailbox"; 242 reg = <0x00 0x31f8a000 0x00 0x200>; 243 #mbox-cells = <1>; 244 ti,mbox-num-users = <4>; 245 ti,mbox-num-fifos = <16>; 246 interrupt-parent = <&main_navss_intr>; 247 }; 248 249 mailbox0_cluster11: mailbox@31f8b000 { 250 compatible = "ti,am654-mailbox"; 251 reg = <0x00 0x31f8b000 0x00 0x200>; 252 #mbox-cells = <1>; 253 ti,mbox-num-users = <4>; 254 ti,mbox-num-fifos = <16>; 255 interrupt-parent = <&main_navss_intr>; 256 }; 257 258 main_ringacc: ringacc@3c000000 { 259 compatible = "ti,am654-navss-ringacc"; 260 reg = <0x0 0x3c000000 0x0 0x400000>, 261 <0x0 0x38000000 0x0 0x400000>, 262 <0x0 0x31120000 0x0 0x100>, 263 <0x0 0x33000000 0x0 0x40000>; 264 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 265 ti,num-rings = <1024>; 266 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 267 ti,sci = <&dmsc>; 268 ti,sci-dev-id = <211>; 269 msi-parent = <&main_udmass_inta>; 270 }; 271 272 main_udmap: dma-controller@31150000 { 273 compatible = "ti,j721e-navss-main-udmap"; 274 reg = <0x0 0x31150000 0x0 0x100>, 275 <0x0 0x34000000 0x0 0x100000>, 276 <0x0 0x35000000 0x0 0x100000>; 277 reg-names = "gcfg", "rchanrt", "tchanrt"; 278 msi-parent = <&main_udmass_inta>; 279 #dma-cells = <1>; 280 281 ti,sci = <&dmsc>; 282 ti,sci-dev-id = <212>; 283 ti,ringacc = <&main_ringacc>; 284 285 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 286 <0x0f>, /* TX_HCHAN */ 287 <0x10>; /* TX_UHCHAN */ 288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 289 <0x0b>, /* RX_HCHAN */ 290 <0x0c>; /* RX_UHCHAN */ 291 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 292 }; 293 294 cpts@310d0000 { 295 compatible = "ti,j721e-cpts"; 296 reg = <0x0 0x310d0000 0x0 0x400>; 297 reg-names = "cpts"; 298 clocks = <&k3_clks 201 1>; 299 clock-names = "cpts"; 300 interrupts-extended = <&main_navss_intr 391>; 301 interrupt-names = "cpts"; 302 ti,cpts-periodic-outputs = <6>; 303 ti,cpts-ext-ts-inputs = <8>; 304 }; 305 }; 306 307 main_pmx0: pinmux@11c000 { 308 compatible = "pinctrl-single"; 309 /* Proxy 0 addressing */ 310 reg = <0x0 0x11c000 0x0 0x2b4>; 311 #pinctrl-cells = <1>; 312 pinctrl-single,register-width = <32>; 313 pinctrl-single,function-mask = <0xffffffff>; 314 }; 315 316 dummy_cmn_refclk: dummy-cmn-refclk { 317 #clock-cells = <0>; 318 compatible = "fixed-clock"; 319 clock-frequency = <100000000>; 320 }; 321 322 dummy_cmn_refclk1: dummy-cmn-refclk1 { 323 #clock-cells = <0>; 324 compatible = "fixed-clock"; 325 clock-frequency = <100000000>; 326 }; 327 328 serdes_wiz0: wiz@5000000 { 329 compatible = "ti,j721e-wiz-16g"; 330 #address-cells = <1>; 331 #size-cells = <1>; 332 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 333 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 334 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 335 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 336 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 337 num-lanes = <2>; 338 #reset-cells = <1>; 339 ranges = <0x5000000 0x0 0x5000000 0x10000>; 340 341 wiz0_pll0_refclk: pll0-refclk { 342 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; 343 #clock-cells = <0>; 344 assigned-clocks = <&wiz0_pll0_refclk>; 345 assigned-clock-parents = <&k3_clks 292 11>; 346 }; 347 348 wiz0_pll1_refclk: pll1-refclk { 349 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; 350 #clock-cells = <0>; 351 assigned-clocks = <&wiz0_pll1_refclk>; 352 assigned-clock-parents = <&k3_clks 292 0>; 353 }; 354 355 wiz0_refclk_dig: refclk-dig { 356 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 357 #clock-cells = <0>; 358 assigned-clocks = <&wiz0_refclk_dig>; 359 assigned-clock-parents = <&k3_clks 292 11>; 360 }; 361 362 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 363 clocks = <&wiz0_refclk_dig>; 364 #clock-cells = <0>; 365 }; 366 367 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 368 clocks = <&wiz0_pll1_refclk>; 369 #clock-cells = <0>; 370 }; 371 372 serdes0: serdes@5000000 { 373 compatible = "ti,sierra-phy-t0"; 374 reg-names = "serdes"; 375 reg = <0x5000000 0x10000>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 resets = <&serdes_wiz0 0>; 379 reset-names = "sierra_reset"; 380 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 381 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 382 }; 383 }; 384 385 serdes_wiz1: wiz@5010000 { 386 compatible = "ti,j721e-wiz-16g"; 387 #address-cells = <1>; 388 #size-cells = <1>; 389 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 390 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; 391 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 392 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 393 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 394 num-lanes = <2>; 395 #reset-cells = <1>; 396 ranges = <0x5010000 0x0 0x5010000 0x10000>; 397 398 wiz1_pll0_refclk: pll0-refclk { 399 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 400 #clock-cells = <0>; 401 assigned-clocks = <&wiz1_pll0_refclk>; 402 assigned-clock-parents = <&k3_clks 293 13>; 403 }; 404 405 wiz1_pll1_refclk: pll1-refclk { 406 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 407 #clock-cells = <0>; 408 assigned-clocks = <&wiz1_pll1_refclk>; 409 assigned-clock-parents = <&k3_clks 293 0>; 410 }; 411 412 wiz1_refclk_dig: refclk-dig { 413 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 414 #clock-cells = <0>; 415 assigned-clocks = <&wiz1_refclk_dig>; 416 assigned-clock-parents = <&k3_clks 293 13>; 417 }; 418 419 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 420 clocks = <&wiz1_refclk_dig>; 421 #clock-cells = <0>; 422 }; 423 424 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 425 clocks = <&wiz1_pll1_refclk>; 426 #clock-cells = <0>; 427 }; 428 429 serdes1: serdes@5010000 { 430 compatible = "ti,sierra-phy-t0"; 431 reg-names = "serdes"; 432 reg = <0x5010000 0x10000>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 resets = <&serdes_wiz1 0>; 436 reset-names = "sierra_reset"; 437 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 438 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 439 }; 440 }; 441 442 serdes_wiz2: wiz@5020000 { 443 compatible = "ti,j721e-wiz-16g"; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 447 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; 448 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 449 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 450 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 451 num-lanes = <2>; 452 #reset-cells = <1>; 453 ranges = <0x5020000 0x0 0x5020000 0x10000>; 454 455 wiz2_pll0_refclk: pll0-refclk { 456 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; 457 #clock-cells = <0>; 458 assigned-clocks = <&wiz2_pll0_refclk>; 459 assigned-clock-parents = <&k3_clks 294 11>; 460 }; 461 462 wiz2_pll1_refclk: pll1-refclk { 463 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; 464 #clock-cells = <0>; 465 assigned-clocks = <&wiz2_pll1_refclk>; 466 assigned-clock-parents = <&k3_clks 294 0>; 467 }; 468 469 wiz2_refclk_dig: refclk-dig { 470 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 471 #clock-cells = <0>; 472 assigned-clocks = <&wiz2_refclk_dig>; 473 assigned-clock-parents = <&k3_clks 294 11>; 474 }; 475 476 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 477 clocks = <&wiz2_refclk_dig>; 478 #clock-cells = <0>; 479 }; 480 481 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 482 clocks = <&wiz2_pll1_refclk>; 483 #clock-cells = <0>; 484 }; 485 486 serdes2: serdes@5020000 { 487 compatible = "ti,sierra-phy-t0"; 488 reg-names = "serdes"; 489 reg = <0x5020000 0x10000>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 resets = <&serdes_wiz2 0>; 493 reset-names = "sierra_reset"; 494 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 495 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 496 }; 497 }; 498 499 serdes_wiz3: wiz@5030000 { 500 compatible = "ti,j721e-wiz-16g"; 501 #address-cells = <1>; 502 #size-cells = <1>; 503 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; 505 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 506 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 507 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 508 num-lanes = <2>; 509 #reset-cells = <1>; 510 ranges = <0x5030000 0x0 0x5030000 0x10000>; 511 512 wiz3_pll0_refclk: pll0-refclk { 513 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; 514 #clock-cells = <0>; 515 assigned-clocks = <&wiz3_pll0_refclk>; 516 assigned-clock-parents = <&k3_clks 295 9>; 517 }; 518 519 wiz3_pll1_refclk: pll1-refclk { 520 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; 521 #clock-cells = <0>; 522 assigned-clocks = <&wiz3_pll1_refclk>; 523 assigned-clock-parents = <&k3_clks 295 0>; 524 }; 525 526 wiz3_refclk_dig: refclk-dig { 527 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 528 #clock-cells = <0>; 529 assigned-clocks = <&wiz3_refclk_dig>; 530 assigned-clock-parents = <&k3_clks 295 9>; 531 }; 532 533 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 534 clocks = <&wiz3_refclk_dig>; 535 #clock-cells = <0>; 536 }; 537 538 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 539 clocks = <&wiz3_pll1_refclk>; 540 #clock-cells = <0>; 541 }; 542 543 serdes3: serdes@5030000 { 544 compatible = "ti,sierra-phy-t0"; 545 reg-names = "serdes"; 546 reg = <0x5030000 0x10000>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 resets = <&serdes_wiz3 0>; 550 reset-names = "sierra_reset"; 551 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 552 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 553 }; 554 }; 555 556 main_uart0: serial@2800000 { 557 compatible = "ti,j721e-uart", "ti,am654-uart"; 558 reg = <0x00 0x02800000 0x00 0x100>; 559 reg-shift = <2>; 560 reg-io-width = <4>; 561 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 562 clock-frequency = <48000000>; 563 current-speed = <115200>; 564 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 146 0>; 566 clock-names = "fclk"; 567 }; 568 569 main_uart1: serial@2810000 { 570 compatible = "ti,j721e-uart", "ti,am654-uart"; 571 reg = <0x00 0x02810000 0x00 0x100>; 572 reg-shift = <2>; 573 reg-io-width = <4>; 574 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 575 clock-frequency = <48000000>; 576 current-speed = <115200>; 577 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 578 clocks = <&k3_clks 278 0>; 579 clock-names = "fclk"; 580 }; 581 582 main_uart2: serial@2820000 { 583 compatible = "ti,j721e-uart", "ti,am654-uart"; 584 reg = <0x00 0x02820000 0x00 0x100>; 585 reg-shift = <2>; 586 reg-io-width = <4>; 587 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 588 clock-frequency = <48000000>; 589 current-speed = <115200>; 590 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 591 clocks = <&k3_clks 279 0>; 592 clock-names = "fclk"; 593 }; 594 595 main_uart3: serial@2830000 { 596 compatible = "ti,j721e-uart", "ti,am654-uart"; 597 reg = <0x00 0x02830000 0x00 0x100>; 598 reg-shift = <2>; 599 reg-io-width = <4>; 600 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 601 clock-frequency = <48000000>; 602 current-speed = <115200>; 603 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 604 clocks = <&k3_clks 280 0>; 605 clock-names = "fclk"; 606 }; 607 608 main_uart4: serial@2840000 { 609 compatible = "ti,j721e-uart", "ti,am654-uart"; 610 reg = <0x00 0x02840000 0x00 0x100>; 611 reg-shift = <2>; 612 reg-io-width = <4>; 613 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 614 clock-frequency = <48000000>; 615 current-speed = <115200>; 616 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 617 clocks = <&k3_clks 281 0>; 618 clock-names = "fclk"; 619 }; 620 621 main_uart5: serial@2850000 { 622 compatible = "ti,j721e-uart", "ti,am654-uart"; 623 reg = <0x00 0x02850000 0x00 0x100>; 624 reg-shift = <2>; 625 reg-io-width = <4>; 626 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 627 clock-frequency = <48000000>; 628 current-speed = <115200>; 629 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 630 clocks = <&k3_clks 282 0>; 631 clock-names = "fclk"; 632 }; 633 634 main_uart6: serial@2860000 { 635 compatible = "ti,j721e-uart", "ti,am654-uart"; 636 reg = <0x00 0x02860000 0x00 0x100>; 637 reg-shift = <2>; 638 reg-io-width = <4>; 639 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 640 clock-frequency = <48000000>; 641 current-speed = <115200>; 642 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 643 clocks = <&k3_clks 283 0>; 644 clock-names = "fclk"; 645 }; 646 647 main_uart7: serial@2870000 { 648 compatible = "ti,j721e-uart", "ti,am654-uart"; 649 reg = <0x00 0x02870000 0x00 0x100>; 650 reg-shift = <2>; 651 reg-io-width = <4>; 652 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 653 clock-frequency = <48000000>; 654 current-speed = <115200>; 655 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 656 clocks = <&k3_clks 284 0>; 657 clock-names = "fclk"; 658 }; 659 660 main_uart8: serial@2880000 { 661 compatible = "ti,j721e-uart", "ti,am654-uart"; 662 reg = <0x00 0x02880000 0x00 0x100>; 663 reg-shift = <2>; 664 reg-io-width = <4>; 665 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 666 clock-frequency = <48000000>; 667 current-speed = <115200>; 668 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 669 clocks = <&k3_clks 285 0>; 670 clock-names = "fclk"; 671 }; 672 673 main_uart9: serial@2890000 { 674 compatible = "ti,j721e-uart", "ti,am654-uart"; 675 reg = <0x00 0x02890000 0x00 0x100>; 676 reg-shift = <2>; 677 reg-io-width = <4>; 678 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 679 clock-frequency = <48000000>; 680 current-speed = <115200>; 681 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 682 clocks = <&k3_clks 286 0>; 683 clock-names = "fclk"; 684 }; 685 686 main_gpio0: gpio@600000 { 687 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 688 reg = <0x0 0x00600000 0x0 0x100>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 interrupt-parent = <&main_gpio_intr>; 692 interrupts = <256>, <257>, <258>, <259>, 693 <260>, <261>, <262>, <263>; 694 interrupt-controller; 695 #interrupt-cells = <2>; 696 ti,ngpio = <128>; 697 ti,davinci-gpio-unbanked = <0>; 698 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 699 clocks = <&k3_clks 105 0>; 700 clock-names = "gpio"; 701 }; 702 703 main_gpio1: gpio@601000 { 704 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 705 reg = <0x0 0x00601000 0x0 0x100>; 706 gpio-controller; 707 #gpio-cells = <2>; 708 interrupt-parent = <&main_gpio_intr>; 709 interrupts = <288>, <289>, <290>; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 ti,ngpio = <36>; 713 ti,davinci-gpio-unbanked = <0>; 714 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 715 clocks = <&k3_clks 106 0>; 716 clock-names = "gpio"; 717 }; 718 719 main_gpio2: gpio@610000 { 720 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 721 reg = <0x0 0x00610000 0x0 0x100>; 722 gpio-controller; 723 #gpio-cells = <2>; 724 interrupt-parent = <&main_gpio_intr>; 725 interrupts = <264>, <265>, <266>, <267>, 726 <268>, <269>, <270>, <271>; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 ti,ngpio = <128>; 730 ti,davinci-gpio-unbanked = <0>; 731 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 732 clocks = <&k3_clks 107 0>; 733 clock-names = "gpio"; 734 }; 735 736 main_gpio3: gpio@611000 { 737 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 738 reg = <0x0 0x00611000 0x0 0x100>; 739 gpio-controller; 740 #gpio-cells = <2>; 741 interrupt-parent = <&main_gpio_intr>; 742 interrupts = <292>, <293>, <294>; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 ti,ngpio = <36>; 746 ti,davinci-gpio-unbanked = <0>; 747 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 748 clocks = <&k3_clks 108 0>; 749 clock-names = "gpio"; 750 }; 751 752 main_gpio4: gpio@620000 { 753 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 754 reg = <0x0 0x00620000 0x0 0x100>; 755 gpio-controller; 756 #gpio-cells = <2>; 757 interrupt-parent = <&main_gpio_intr>; 758 interrupts = <272>, <273>, <274>, <275>, 759 <276>, <277>, <278>, <279>; 760 interrupt-controller; 761 #interrupt-cells = <2>; 762 ti,ngpio = <128>; 763 ti,davinci-gpio-unbanked = <0>; 764 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 765 clocks = <&k3_clks 109 0>; 766 clock-names = "gpio"; 767 }; 768 769 main_gpio5: gpio@621000 { 770 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 771 reg = <0x0 0x00621000 0x0 0x100>; 772 gpio-controller; 773 #gpio-cells = <2>; 774 interrupt-parent = <&main_gpio_intr>; 775 interrupts = <296>, <297>, <298>; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 ti,ngpio = <36>; 779 ti,davinci-gpio-unbanked = <0>; 780 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 781 clocks = <&k3_clks 110 0>; 782 clock-names = "gpio"; 783 }; 784 785 main_gpio6: gpio@630000 { 786 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 787 reg = <0x0 0x00630000 0x0 0x100>; 788 gpio-controller; 789 #gpio-cells = <2>; 790 interrupt-parent = <&main_gpio_intr>; 791 interrupts = <280>, <281>, <282>, <283>, 792 <284>, <285>, <286>, <287>; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 ti,ngpio = <128>; 796 ti,davinci-gpio-unbanked = <0>; 797 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 798 clocks = <&k3_clks 111 0>; 799 clock-names = "gpio"; 800 }; 801 802 main_gpio7: gpio@631000 { 803 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 804 reg = <0x0 0x00631000 0x0 0x100>; 805 gpio-controller; 806 #gpio-cells = <2>; 807 interrupt-parent = <&main_gpio_intr>; 808 interrupts = <300>, <301>, <302>; 809 interrupt-controller; 810 #interrupt-cells = <2>; 811 ti,ngpio = <36>; 812 ti,davinci-gpio-unbanked = <0>; 813 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 814 clocks = <&k3_clks 112 0>; 815 clock-names = "gpio"; 816 }; 817 818 main_sdhci0: sdhci@4f80000 { 819 compatible = "ti,j721e-sdhci-8bit"; 820 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 821 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 822 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 823 clock-names = "clk_xin", "clk_ahb"; 824 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 825 assigned-clocks = <&k3_clks 91 1>; 826 assigned-clock-parents = <&k3_clks 91 2>; 827 bus-width = <8>; 828 mmc-hs400-1_8v; 829 mmc-ddr-1_8v; 830 ti,otap-del-sel = <0x2>; 831 ti,trm-icp = <0x8>; 832 ti,strobe-sel = <0x77>; 833 dma-coherent; 834 }; 835 836 main_sdhci1: sdhci@4fb0000 { 837 compatible = "ti,j721e-sdhci-4bit"; 838 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 839 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 840 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 841 clock-names = "clk_xin", "clk_ahb"; 842 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 843 assigned-clocks = <&k3_clks 92 0>; 844 assigned-clock-parents = <&k3_clks 92 1>; 845 ti,otap-del-sel = <0x2>; 846 ti,trm-icp = <0x8>; 847 ti,clkbuf-sel = <0x7>; 848 dma-coherent; 849 no-1-8-v; 850 }; 851 852 main_sdhci2: sdhci@4f98000 { 853 compatible = "ti,j721e-sdhci-4bit"; 854 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 855 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 856 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 857 clock-names = "clk_xin", "clk_ahb"; 858 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 859 assigned-clocks = <&k3_clks 93 0>; 860 assigned-clock-parents = <&k3_clks 93 1>; 861 ti,otap-del-sel = <0x2>; 862 ti,trm-icp = <0x8>; 863 ti,clkbuf-sel = <0x7>; 864 dma-coherent; 865 no-1-8-v; 866 }; 867 868 usbss0: cdns_usb@4104000 { 869 compatible = "ti,j721e-usb"; 870 reg = <0x00 0x4104000 0x00 0x100>; 871 dma-coherent; 872 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 874 clock-names = "ref", "lpm"; 875 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 876 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 877 #address-cells = <2>; 878 #size-cells = <2>; 879 ranges; 880 881 usb0: usb@6000000 { 882 compatible = "cdns,usb3"; 883 reg = <0x00 0x6000000 0x00 0x10000>, 884 <0x00 0x6010000 0x00 0x10000>, 885 <0x00 0x6020000 0x00 0x10000>; 886 reg-names = "otg", "xhci", "dev"; 887 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 888 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 889 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 890 interrupt-names = "host", 891 "peripheral", 892 "otg"; 893 maximum-speed = "super-speed"; 894 dr_mode = "otg"; 895 }; 896 }; 897 898 usbss1: cdns_usb@4114000 { 899 compatible = "ti,j721e-usb"; 900 reg = <0x00 0x4114000 0x00 0x100>; 901 dma-coherent; 902 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 904 clock-names = "ref", "lpm"; 905 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 906 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 907 #address-cells = <2>; 908 #size-cells = <2>; 909 ranges; 910 911 usb1: usb@6400000 { 912 compatible = "cdns,usb3"; 913 reg = <0x00 0x6400000 0x00 0x10000>, 914 <0x00 0x6410000 0x00 0x10000>, 915 <0x00 0x6420000 0x00 0x10000>; 916 reg-names = "otg", "xhci", "dev"; 917 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 918 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 919 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 920 interrupt-names = "host", 921 "peripheral", 922 "otg"; 923 maximum-speed = "super-speed"; 924 dr_mode = "otg"; 925 }; 926 }; 927 928 main_i2c0: i2c@2000000 { 929 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 930 reg = <0x0 0x2000000 0x0 0x100>; 931 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 clock-names = "fck"; 935 clocks = <&k3_clks 187 0>; 936 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 937 }; 938 939 main_i2c1: i2c@2010000 { 940 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 941 reg = <0x0 0x2010000 0x0 0x100>; 942 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 clock-names = "fck"; 946 clocks = <&k3_clks 188 0>; 947 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 948 }; 949 950 main_i2c2: i2c@2020000 { 951 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 952 reg = <0x0 0x2020000 0x0 0x100>; 953 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 clock-names = "fck"; 957 clocks = <&k3_clks 189 0>; 958 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 959 }; 960 961 main_i2c3: i2c@2030000 { 962 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 963 reg = <0x0 0x2030000 0x0 0x100>; 964 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 clock-names = "fck"; 968 clocks = <&k3_clks 190 0>; 969 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 970 }; 971 972 main_i2c4: i2c@2040000 { 973 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 974 reg = <0x0 0x2040000 0x0 0x100>; 975 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 clock-names = "fck"; 979 clocks = <&k3_clks 191 0>; 980 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 981 }; 982 983 main_i2c5: i2c@2050000 { 984 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 985 reg = <0x0 0x2050000 0x0 0x100>; 986 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clock-names = "fck"; 990 clocks = <&k3_clks 192 0>; 991 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 992 }; 993 994 main_i2c6: i2c@2060000 { 995 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 996 reg = <0x0 0x2060000 0x0 0x100>; 997 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 clock-names = "fck"; 1001 clocks = <&k3_clks 193 0>; 1002 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1003 }; 1004 1005 ufs_wrapper: ufs-wrapper@4e80000 { 1006 compatible = "ti,j721e-ufs"; 1007 reg = <0x0 0x4e80000 0x0 0x100>; 1008 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1009 clocks = <&k3_clks 277 1>; 1010 assigned-clocks = <&k3_clks 277 1>; 1011 assigned-clock-parents = <&k3_clks 277 4>; 1012 ranges; 1013 #address-cells = <2>; 1014 #size-cells = <2>; 1015 1016 ufs@4e84000 { 1017 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1018 reg = <0x0 0x4e84000 0x0 0x10000>; 1019 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1020 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1021 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1022 clock-names = "core_clk", "phy_clk", "ref_clk"; 1023 dma-coherent; 1024 }; 1025 }; 1026 1027 dss: dss@04a00000 { 1028 compatible = "ti,j721e-dss"; 1029 reg = 1030 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1031 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1032 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1033 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1034 1035 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1036 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1037 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1038 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1039 1040 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1041 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1042 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1043 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1044 1045 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1046 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1047 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1048 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1049 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1050 1051 reg-names = "common_m", "common_s0", 1052 "common_s1", "common_s2", 1053 "vidl1", "vidl2","vid1","vid2", 1054 "ovr1", "ovr2", "ovr3", "ovr4", 1055 "vp1", "vp2", "vp3", "vp4", 1056 "wb"; 1057 1058 clocks = <&k3_clks 152 0>, 1059 <&k3_clks 152 1>, 1060 <&k3_clks 152 4>, 1061 <&k3_clks 152 9>, 1062 <&k3_clks 152 13>; 1063 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1064 1065 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1066 1067 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1071 interrupt-names = "common_m", 1072 "common_s0", 1073 "common_s1", 1074 "common_s2"; 1075 1076 status = "disabled"; 1077 1078 dss_ports: ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 }; 1082 }; 1083 1084 mcasp0: mcasp@2b00000 { 1085 compatible = "ti,am33xx-mcasp-audio"; 1086 reg = <0x0 0x02b00000 0x0 0x2000>, 1087 <0x0 0x02b08000 0x0 0x1000>; 1088 reg-names = "mpu","dat"; 1089 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1091 interrupt-names = "tx", "rx"; 1092 1093 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1094 dma-names = "tx", "rx"; 1095 1096 clocks = <&k3_clks 174 1>; 1097 clock-names = "fck"; 1098 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1099 1100 status = "disabled"; 1101 }; 1102 1103 mcasp1: mcasp@2b10000 { 1104 compatible = "ti,am33xx-mcasp-audio"; 1105 reg = <0x0 0x02b10000 0x0 0x2000>, 1106 <0x0 0x02b18000 0x0 0x1000>; 1107 reg-names = "mpu","dat"; 1108 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupt-names = "tx", "rx"; 1111 1112 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1113 dma-names = "tx", "rx"; 1114 1115 clocks = <&k3_clks 175 1>; 1116 clock-names = "fck"; 1117 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1118 1119 status = "disabled"; 1120 }; 1121 1122 mcasp2: mcasp@2b20000 { 1123 compatible = "ti,am33xx-mcasp-audio"; 1124 reg = <0x0 0x02b20000 0x0 0x2000>, 1125 <0x0 0x02b28000 0x0 0x1000>; 1126 reg-names = "mpu","dat"; 1127 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1129 interrupt-names = "tx", "rx"; 1130 1131 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1132 dma-names = "tx", "rx"; 1133 1134 clocks = <&k3_clks 176 1>; 1135 clock-names = "fck"; 1136 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1137 1138 status = "disabled"; 1139 }; 1140 1141 mcasp3: mcasp@2b30000 { 1142 compatible = "ti,am33xx-mcasp-audio"; 1143 reg = <0x0 0x02b30000 0x0 0x2000>, 1144 <0x0 0x02b38000 0x0 0x1000>; 1145 reg-names = "mpu","dat"; 1146 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1148 interrupt-names = "tx", "rx"; 1149 1150 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1151 dma-names = "tx", "rx"; 1152 1153 clocks = <&k3_clks 177 1>; 1154 clock-names = "fck"; 1155 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1156 1157 status = "disabled"; 1158 }; 1159 1160 mcasp4: mcasp@2b40000 { 1161 compatible = "ti,am33xx-mcasp-audio"; 1162 reg = <0x0 0x02b40000 0x0 0x2000>, 1163 <0x0 0x02b48000 0x0 0x1000>; 1164 reg-names = "mpu","dat"; 1165 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1167 interrupt-names = "tx", "rx"; 1168 1169 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1170 dma-names = "tx", "rx"; 1171 1172 clocks = <&k3_clks 178 1>; 1173 clock-names = "fck"; 1174 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 mcasp5: mcasp@2b50000 { 1180 compatible = "ti,am33xx-mcasp-audio"; 1181 reg = <0x0 0x02b50000 0x0 0x2000>, 1182 <0x0 0x02b58000 0x0 0x1000>; 1183 reg-names = "mpu","dat"; 1184 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1186 interrupt-names = "tx", "rx"; 1187 1188 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1189 dma-names = "tx", "rx"; 1190 1191 clocks = <&k3_clks 179 1>; 1192 clock-names = "fck"; 1193 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1194 1195 status = "disabled"; 1196 }; 1197 1198 mcasp6: mcasp@2b60000 { 1199 compatible = "ti,am33xx-mcasp-audio"; 1200 reg = <0x0 0x02b60000 0x0 0x2000>, 1201 <0x0 0x02b68000 0x0 0x1000>; 1202 reg-names = "mpu","dat"; 1203 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1205 interrupt-names = "tx", "rx"; 1206 1207 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1208 dma-names = "tx", "rx"; 1209 1210 clocks = <&k3_clks 180 1>; 1211 clock-names = "fck"; 1212 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1213 1214 status = "disabled"; 1215 }; 1216 1217 mcasp7: mcasp@2b70000 { 1218 compatible = "ti,am33xx-mcasp-audio"; 1219 reg = <0x0 0x02b70000 0x0 0x2000>, 1220 <0x0 0x02b78000 0x0 0x1000>; 1221 reg-names = "mpu","dat"; 1222 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "tx", "rx"; 1225 1226 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1227 dma-names = "tx", "rx"; 1228 1229 clocks = <&k3_clks 181 1>; 1230 clock-names = "fck"; 1231 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1232 1233 status = "disabled"; 1234 }; 1235 1236 mcasp8: mcasp@2b80000 { 1237 compatible = "ti,am33xx-mcasp-audio"; 1238 reg = <0x0 0x02b80000 0x0 0x2000>, 1239 <0x0 0x02b88000 0x0 0x1000>; 1240 reg-names = "mpu","dat"; 1241 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1243 interrupt-names = "tx", "rx"; 1244 1245 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1246 dma-names = "tx", "rx"; 1247 1248 clocks = <&k3_clks 182 1>; 1249 clock-names = "fck"; 1250 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1251 1252 status = "disabled"; 1253 }; 1254 1255 mcasp9: mcasp@2b90000 { 1256 compatible = "ti,am33xx-mcasp-audio"; 1257 reg = <0x0 0x02b90000 0x0 0x2000>, 1258 <0x0 0x02b98000 0x0 0x1000>; 1259 reg-names = "mpu","dat"; 1260 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1262 interrupt-names = "tx", "rx"; 1263 1264 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1265 dma-names = "tx", "rx"; 1266 1267 clocks = <&k3_clks 183 1>; 1268 clock-names = "fck"; 1269 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1270 1271 status = "disabled"; 1272 }; 1273 1274 mcasp10: mcasp@2ba0000 { 1275 compatible = "ti,am33xx-mcasp-audio"; 1276 reg = <0x0 0x02ba0000 0x0 0x2000>, 1277 <0x0 0x02ba8000 0x0 0x1000>; 1278 reg-names = "mpu","dat"; 1279 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1281 interrupt-names = "tx", "rx"; 1282 1283 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1284 dma-names = "tx", "rx"; 1285 1286 clocks = <&k3_clks 184 1>; 1287 clock-names = "fck"; 1288 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1289 1290 status = "disabled"; 1291 }; 1292 1293 mcasp11: mcasp@2bb0000 { 1294 compatible = "ti,am33xx-mcasp-audio"; 1295 reg = <0x0 0x02bb0000 0x0 0x2000>, 1296 <0x0 0x02bb8000 0x0 0x1000>; 1297 reg-names = "mpu","dat"; 1298 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1300 interrupt-names = "tx", "rx"; 1301 1302 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1303 dma-names = "tx", "rx"; 1304 1305 clocks = <&k3_clks 185 1>; 1306 clock-names = "fck"; 1307 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1308 1309 status = "disabled"; 1310 }; 1311 1312 watchdog0: watchdog@2200000 { 1313 compatible = "ti,j7-rti-wdt"; 1314 reg = <0x0 0x2200000 0x0 0x100>; 1315 clocks = <&k3_clks 252 1>; 1316 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1317 assigned-clocks = <&k3_clks 252 1>; 1318 assigned-clock-parents = <&k3_clks 252 5>; 1319 }; 1320 1321 watchdog1: watchdog@2210000 { 1322 compatible = "ti,j7-rti-wdt"; 1323 reg = <0x0 0x2210000 0x0 0x100>; 1324 clocks = <&k3_clks 253 1>; 1325 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1326 assigned-clocks = <&k3_clks 253 1>; 1327 assigned-clock-parents = <&k3_clks 253 5>; 1328 }; 1329}; 1330