1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11&cbass_main { 12 msmc_ram: sram@70000000 { 13 compatible = "mmio-sram"; 14 reg = <0x0 0x70000000 0x0 0x800000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x0 0x0 0x70000000 0x800000>; 18 19 atf-sram@0 { 20 reg = <0x0 0x20000>; 21 }; 22 }; 23 24 scm_conf: scm-conf@100000 { 25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x0 0x0 0x00100000 0x1c000>; 30 31 serdes_ln_ctrl: mux@4080 { 32 compatible = "mmio-mux"; 33 reg = <0x00004080 0x50>; 34 #mux-control-cells = <1>; 35 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 36 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 37 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 38 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 39 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 40 /* SERDES4 lane0/1/2/3 select */ 41 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 42 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 43 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 44 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 45 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 46 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 47 }; 48 49 usb_serdes_mux: mux-controller@4000 { 50 compatible = "mmio-mux"; 51 #mux-control-cells = <1>; 52 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 53 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 54 }; 55 }; 56 57 gic500: interrupt-controller@1800000 { 58 compatible = "arm,gic-v3"; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 #interrupt-cells = <3>; 63 interrupt-controller; 64 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 65 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 66 67 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 68 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 69 70 gic_its: msi-controller@1820000 { 71 compatible = "arm,gic-v3-its"; 72 reg = <0x00 0x01820000 0x00 0x10000>; 73 socionext,synquacer-pre-its = <0x1000000 0x400000>; 74 msi-controller; 75 #msi-cells = <1>; 76 }; 77 }; 78 79 main_gpio_intr: interrupt-controller0 { 80 compatible = "ti,sci-intr"; 81 ti,intr-trigger-type = <1>; 82 interrupt-controller; 83 interrupt-parent = <&gic500>; 84 #interrupt-cells = <1>; 85 ti,sci = <&dmsc>; 86 ti,sci-dev-id = <131>; 87 ti,interrupt-ranges = <8 392 56>; 88 }; 89 90 main-navss { 91 compatible = "simple-mfd"; 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 dma-coherent; 96 dma-ranges; 97 98 ti,sci-dev-id = <199>; 99 100 main_navss_intr: interrupt-controller1 { 101 compatible = "ti,sci-intr"; 102 ti,intr-trigger-type = <4>; 103 interrupt-controller; 104 interrupt-parent = <&gic500>; 105 #interrupt-cells = <1>; 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <213>; 108 ti,interrupt-ranges = <0 64 64>, 109 <64 448 64>, 110 <128 672 64>; 111 }; 112 113 main_udmass_inta: interrupt-controller@33d00000 { 114 compatible = "ti,sci-inta"; 115 reg = <0x0 0x33d00000 0x0 0x100000>; 116 interrupt-controller; 117 interrupt-parent = <&main_navss_intr>; 118 msi-controller; 119 #interrupt-cells = <0>; 120 ti,sci = <&dmsc>; 121 ti,sci-dev-id = <209>; 122 ti,interrupt-ranges = <0 0 256>; 123 }; 124 125 secure_proxy_main: mailbox@32c00000 { 126 compatible = "ti,am654-secure-proxy"; 127 #mbox-cells = <1>; 128 reg-names = "target_data", "rt", "scfg"; 129 reg = <0x00 0x32c00000 0x00 0x100000>, 130 <0x00 0x32400000 0x00 0x100000>, 131 <0x00 0x32800000 0x00 0x100000>; 132 interrupt-names = "rx_011"; 133 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 136 smmu0: iommu@36600000 { 137 compatible = "arm,smmu-v3"; 138 reg = <0x0 0x36600000 0x0 0x100000>; 139 interrupt-parent = <&gic500>; 140 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 141 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 142 interrupt-names = "eventq", "gerror"; 143 #iommu-cells = <1>; 144 }; 145 146 hwspinlock: spinlock@30e00000 { 147 compatible = "ti,am654-hwspinlock"; 148 reg = <0x00 0x30e00000 0x00 0x1000>; 149 #hwlock-cells = <1>; 150 }; 151 152 mailbox0_cluster0: mailbox@31f80000 { 153 compatible = "ti,am654-mailbox"; 154 reg = <0x00 0x31f80000 0x00 0x200>; 155 #mbox-cells = <1>; 156 ti,mbox-num-users = <4>; 157 ti,mbox-num-fifos = <16>; 158 interrupt-parent = <&main_navss_intr>; 159 }; 160 161 mailbox0_cluster1: mailbox@31f81000 { 162 compatible = "ti,am654-mailbox"; 163 reg = <0x00 0x31f81000 0x00 0x200>; 164 #mbox-cells = <1>; 165 ti,mbox-num-users = <4>; 166 ti,mbox-num-fifos = <16>; 167 interrupt-parent = <&main_navss_intr>; 168 }; 169 170 mailbox0_cluster2: mailbox@31f82000 { 171 compatible = "ti,am654-mailbox"; 172 reg = <0x00 0x31f82000 0x00 0x200>; 173 #mbox-cells = <1>; 174 ti,mbox-num-users = <4>; 175 ti,mbox-num-fifos = <16>; 176 interrupt-parent = <&main_navss_intr>; 177 }; 178 179 mailbox0_cluster3: mailbox@31f83000 { 180 compatible = "ti,am654-mailbox"; 181 reg = <0x00 0x31f83000 0x00 0x200>; 182 #mbox-cells = <1>; 183 ti,mbox-num-users = <4>; 184 ti,mbox-num-fifos = <16>; 185 interrupt-parent = <&main_navss_intr>; 186 }; 187 188 mailbox0_cluster4: mailbox@31f84000 { 189 compatible = "ti,am654-mailbox"; 190 reg = <0x00 0x31f84000 0x00 0x200>; 191 #mbox-cells = <1>; 192 ti,mbox-num-users = <4>; 193 ti,mbox-num-fifos = <16>; 194 interrupt-parent = <&main_navss_intr>; 195 }; 196 197 mailbox0_cluster5: mailbox@31f85000 { 198 compatible = "ti,am654-mailbox"; 199 reg = <0x00 0x31f85000 0x00 0x200>; 200 #mbox-cells = <1>; 201 ti,mbox-num-users = <4>; 202 ti,mbox-num-fifos = <16>; 203 interrupt-parent = <&main_navss_intr>; 204 }; 205 206 mailbox0_cluster6: mailbox@31f86000 { 207 compatible = "ti,am654-mailbox"; 208 reg = <0x00 0x31f86000 0x00 0x200>; 209 #mbox-cells = <1>; 210 ti,mbox-num-users = <4>; 211 ti,mbox-num-fifos = <16>; 212 interrupt-parent = <&main_navss_intr>; 213 }; 214 215 mailbox0_cluster7: mailbox@31f87000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f87000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 }; 223 224 mailbox0_cluster8: mailbox@31f88000 { 225 compatible = "ti,am654-mailbox"; 226 reg = <0x00 0x31f88000 0x00 0x200>; 227 #mbox-cells = <1>; 228 ti,mbox-num-users = <4>; 229 ti,mbox-num-fifos = <16>; 230 interrupt-parent = <&main_navss_intr>; 231 }; 232 233 mailbox0_cluster9: mailbox@31f89000 { 234 compatible = "ti,am654-mailbox"; 235 reg = <0x00 0x31f89000 0x00 0x200>; 236 #mbox-cells = <1>; 237 ti,mbox-num-users = <4>; 238 ti,mbox-num-fifos = <16>; 239 interrupt-parent = <&main_navss_intr>; 240 }; 241 242 mailbox0_cluster10: mailbox@31f8a000 { 243 compatible = "ti,am654-mailbox"; 244 reg = <0x00 0x31f8a000 0x00 0x200>; 245 #mbox-cells = <1>; 246 ti,mbox-num-users = <4>; 247 ti,mbox-num-fifos = <16>; 248 interrupt-parent = <&main_navss_intr>; 249 }; 250 251 mailbox0_cluster11: mailbox@31f8b000 { 252 compatible = "ti,am654-mailbox"; 253 reg = <0x00 0x31f8b000 0x00 0x200>; 254 #mbox-cells = <1>; 255 ti,mbox-num-users = <4>; 256 ti,mbox-num-fifos = <16>; 257 interrupt-parent = <&main_navss_intr>; 258 }; 259 260 main_ringacc: ringacc@3c000000 { 261 compatible = "ti,am654-navss-ringacc"; 262 reg = <0x0 0x3c000000 0x0 0x400000>, 263 <0x0 0x38000000 0x0 0x400000>, 264 <0x0 0x31120000 0x0 0x100>, 265 <0x0 0x33000000 0x0 0x40000>; 266 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 267 ti,num-rings = <1024>; 268 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 269 ti,sci = <&dmsc>; 270 ti,sci-dev-id = <211>; 271 msi-parent = <&main_udmass_inta>; 272 }; 273 274 main_udmap: dma-controller@31150000 { 275 compatible = "ti,j721e-navss-main-udmap"; 276 reg = <0x0 0x31150000 0x0 0x100>, 277 <0x0 0x34000000 0x0 0x100000>, 278 <0x0 0x35000000 0x0 0x100000>; 279 reg-names = "gcfg", "rchanrt", "tchanrt"; 280 msi-parent = <&main_udmass_inta>; 281 #dma-cells = <1>; 282 283 ti,sci = <&dmsc>; 284 ti,sci-dev-id = <212>; 285 ti,ringacc = <&main_ringacc>; 286 287 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 288 <0x0f>, /* TX_HCHAN */ 289 <0x10>; /* TX_UHCHAN */ 290 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 291 <0x0b>, /* RX_HCHAN */ 292 <0x0c>; /* RX_UHCHAN */ 293 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 294 }; 295 296 cpts@310d0000 { 297 compatible = "ti,j721e-cpts"; 298 reg = <0x0 0x310d0000 0x0 0x400>; 299 reg-names = "cpts"; 300 clocks = <&k3_clks 201 1>; 301 clock-names = "cpts"; 302 interrupts-extended = <&main_navss_intr 391>; 303 interrupt-names = "cpts"; 304 ti,cpts-periodic-outputs = <6>; 305 ti,cpts-ext-ts-inputs = <8>; 306 }; 307 }; 308 309 main_crypto: crypto@4e00000 { 310 compatible = "ti,j721e-sa2ul"; 311 reg = <0x0 0x4e00000 0x0 0x1200>; 312 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 313 #address-cells = <2>; 314 #size-cells = <2>; 315 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 316 317 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 318 <&main_udmap 0x4001>; 319 dma-names = "tx", "rx1", "rx2"; 320 dma-coherent; 321 322 rng: rng@4e10000 { 323 compatible = "inside-secure,safexcel-eip76"; 324 reg = <0x0 0x4e10000 0x0 0x7d>; 325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 264 1>; 327 }; 328 }; 329 330 main_pmx0: pinctrl@11c000 { 331 compatible = "pinctrl-single"; 332 /* Proxy 0 addressing */ 333 reg = <0x0 0x11c000 0x0 0x2b4>; 334 #pinctrl-cells = <1>; 335 pinctrl-single,register-width = <32>; 336 pinctrl-single,function-mask = <0xffffffff>; 337 }; 338 339 dummy_cmn_refclk: dummy-cmn-refclk { 340 #clock-cells = <0>; 341 compatible = "fixed-clock"; 342 clock-frequency = <100000000>; 343 }; 344 345 dummy_cmn_refclk1: dummy-cmn-refclk1 { 346 #clock-cells = <0>; 347 compatible = "fixed-clock"; 348 clock-frequency = <100000000>; 349 }; 350 351 serdes_wiz0: wiz@5000000 { 352 compatible = "ti,j721e-wiz-16g"; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 357 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 358 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 359 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 360 num-lanes = <2>; 361 #reset-cells = <1>; 362 ranges = <0x5000000 0x0 0x5000000 0x10000>; 363 364 wiz0_pll0_refclk: pll0-refclk { 365 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; 366 #clock-cells = <0>; 367 assigned-clocks = <&wiz0_pll0_refclk>; 368 assigned-clock-parents = <&k3_clks 292 11>; 369 }; 370 371 wiz0_pll1_refclk: pll1-refclk { 372 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; 373 #clock-cells = <0>; 374 assigned-clocks = <&wiz0_pll1_refclk>; 375 assigned-clock-parents = <&k3_clks 292 0>; 376 }; 377 378 wiz0_refclk_dig: refclk-dig { 379 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 380 #clock-cells = <0>; 381 assigned-clocks = <&wiz0_refclk_dig>; 382 assigned-clock-parents = <&k3_clks 292 11>; 383 }; 384 385 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 386 clocks = <&wiz0_refclk_dig>; 387 #clock-cells = <0>; 388 }; 389 390 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 391 clocks = <&wiz0_pll1_refclk>; 392 #clock-cells = <0>; 393 }; 394 395 serdes0: serdes@5000000 { 396 compatible = "ti,sierra-phy-t0"; 397 reg-names = "serdes"; 398 reg = <0x5000000 0x10000>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 resets = <&serdes_wiz0 0>; 402 reset-names = "sierra_reset"; 403 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 404 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 405 }; 406 }; 407 408 serdes_wiz1: wiz@5010000 { 409 compatible = "ti,j721e-wiz-16g"; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 413 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; 414 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 415 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 416 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 417 num-lanes = <2>; 418 #reset-cells = <1>; 419 ranges = <0x5010000 0x0 0x5010000 0x10000>; 420 421 wiz1_pll0_refclk: pll0-refclk { 422 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 423 #clock-cells = <0>; 424 assigned-clocks = <&wiz1_pll0_refclk>; 425 assigned-clock-parents = <&k3_clks 293 13>; 426 }; 427 428 wiz1_pll1_refclk: pll1-refclk { 429 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 430 #clock-cells = <0>; 431 assigned-clocks = <&wiz1_pll1_refclk>; 432 assigned-clock-parents = <&k3_clks 293 0>; 433 }; 434 435 wiz1_refclk_dig: refclk-dig { 436 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 437 #clock-cells = <0>; 438 assigned-clocks = <&wiz1_refclk_dig>; 439 assigned-clock-parents = <&k3_clks 293 13>; 440 }; 441 442 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 443 clocks = <&wiz1_refclk_dig>; 444 #clock-cells = <0>; 445 }; 446 447 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 448 clocks = <&wiz1_pll1_refclk>; 449 #clock-cells = <0>; 450 }; 451 452 serdes1: serdes@5010000 { 453 compatible = "ti,sierra-phy-t0"; 454 reg-names = "serdes"; 455 reg = <0x5010000 0x10000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 resets = <&serdes_wiz1 0>; 459 reset-names = "sierra_reset"; 460 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 461 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 462 }; 463 }; 464 465 serdes_wiz2: wiz@5020000 { 466 compatible = "ti,j721e-wiz-16g"; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 470 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; 471 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 472 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 473 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 474 num-lanes = <2>; 475 #reset-cells = <1>; 476 ranges = <0x5020000 0x0 0x5020000 0x10000>; 477 478 wiz2_pll0_refclk: pll0-refclk { 479 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; 480 #clock-cells = <0>; 481 assigned-clocks = <&wiz2_pll0_refclk>; 482 assigned-clock-parents = <&k3_clks 294 11>; 483 }; 484 485 wiz2_pll1_refclk: pll1-refclk { 486 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; 487 #clock-cells = <0>; 488 assigned-clocks = <&wiz2_pll1_refclk>; 489 assigned-clock-parents = <&k3_clks 294 0>; 490 }; 491 492 wiz2_refclk_dig: refclk-dig { 493 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 494 #clock-cells = <0>; 495 assigned-clocks = <&wiz2_refclk_dig>; 496 assigned-clock-parents = <&k3_clks 294 11>; 497 }; 498 499 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 500 clocks = <&wiz2_refclk_dig>; 501 #clock-cells = <0>; 502 }; 503 504 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 505 clocks = <&wiz2_pll1_refclk>; 506 #clock-cells = <0>; 507 }; 508 509 serdes2: serdes@5020000 { 510 compatible = "ti,sierra-phy-t0"; 511 reg-names = "serdes"; 512 reg = <0x5020000 0x10000>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 resets = <&serdes_wiz2 0>; 516 reset-names = "sierra_reset"; 517 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 518 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 519 }; 520 }; 521 522 serdes_wiz3: wiz@5030000 { 523 compatible = "ti,j721e-wiz-16g"; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 527 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; 528 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 529 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 530 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 531 num-lanes = <2>; 532 #reset-cells = <1>; 533 ranges = <0x5030000 0x0 0x5030000 0x10000>; 534 535 wiz3_pll0_refclk: pll0-refclk { 536 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; 537 #clock-cells = <0>; 538 assigned-clocks = <&wiz3_pll0_refclk>; 539 assigned-clock-parents = <&k3_clks 295 9>; 540 }; 541 542 wiz3_pll1_refclk: pll1-refclk { 543 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; 544 #clock-cells = <0>; 545 assigned-clocks = <&wiz3_pll1_refclk>; 546 assigned-clock-parents = <&k3_clks 295 0>; 547 }; 548 549 wiz3_refclk_dig: refclk-dig { 550 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 551 #clock-cells = <0>; 552 assigned-clocks = <&wiz3_refclk_dig>; 553 assigned-clock-parents = <&k3_clks 295 9>; 554 }; 555 556 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 557 clocks = <&wiz3_refclk_dig>; 558 #clock-cells = <0>; 559 }; 560 561 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 562 clocks = <&wiz3_pll1_refclk>; 563 #clock-cells = <0>; 564 }; 565 566 serdes3: serdes@5030000 { 567 compatible = "ti,sierra-phy-t0"; 568 reg-names = "serdes"; 569 reg = <0x5030000 0x10000>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 resets = <&serdes_wiz3 0>; 573 reset-names = "sierra_reset"; 574 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 575 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 576 }; 577 }; 578 579 pcie0_rc: pcie@2900000 { 580 compatible = "ti,j721e-pcie-host"; 581 reg = <0x00 0x02900000 0x00 0x1000>, 582 <0x00 0x02907000 0x00 0x400>, 583 <0x00 0x0d000000 0x00 0x00800000>, 584 <0x00 0x10000000 0x00 0x00001000>; 585 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 586 interrupt-names = "link_state"; 587 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 588 device_type = "pci"; 589 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 590 max-link-speed = <3>; 591 num-lanes = <2>; 592 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 593 clocks = <&k3_clks 239 1>; 594 clock-names = "fck"; 595 #address-cells = <3>; 596 #size-cells = <2>; 597 bus-range = <0x0 0xf>; 598 vendor-id = <0x104c>; 599 device-id = <0xb00d>; 600 msi-map = <0x0 &gic_its 0x0 0x10000>; 601 dma-coherent; 602 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 603 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 604 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 605 }; 606 607 pcie0_ep: pcie-ep@2900000 { 608 compatible = "ti,j721e-pcie-ep"; 609 reg = <0x00 0x02900000 0x00 0x1000>, 610 <0x00 0x02907000 0x00 0x400>, 611 <0x00 0x0d000000 0x00 0x00800000>, 612 <0x00 0x10000000 0x00 0x08000000>; 613 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 614 interrupt-names = "link_state"; 615 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 616 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 617 max-link-speed = <3>; 618 num-lanes = <2>; 619 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 620 clocks = <&k3_clks 239 1>; 621 clock-names = "fck"; 622 max-functions = /bits/ 8 <6>; 623 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 624 dma-coherent; 625 }; 626 627 pcie1_rc: pcie@2910000 { 628 compatible = "ti,j721e-pcie-host"; 629 reg = <0x00 0x02910000 0x00 0x1000>, 630 <0x00 0x02917000 0x00 0x400>, 631 <0x00 0x0d800000 0x00 0x00800000>, 632 <0x00 0x18000000 0x00 0x00001000>; 633 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 634 interrupt-names = "link_state"; 635 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 636 device_type = "pci"; 637 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 638 max-link-speed = <3>; 639 num-lanes = <2>; 640 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 641 clocks = <&k3_clks 240 1>; 642 clock-names = "fck"; 643 #address-cells = <3>; 644 #size-cells = <2>; 645 bus-range = <0x0 0xf>; 646 vendor-id = <0x104c>; 647 device-id = <0xb00d>; 648 msi-map = <0x0 &gic_its 0x10000 0x10000>; 649 dma-coherent; 650 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 651 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 652 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 653 }; 654 655 pcie1_ep: pcie-ep@2910000 { 656 compatible = "ti,j721e-pcie-ep"; 657 reg = <0x00 0x02910000 0x00 0x1000>, 658 <0x00 0x02917000 0x00 0x400>, 659 <0x00 0x0d800000 0x00 0x00800000>, 660 <0x00 0x18000000 0x00 0x08000000>; 661 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 662 interrupt-names = "link_state"; 663 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 664 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 665 max-link-speed = <3>; 666 num-lanes = <2>; 667 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 668 clocks = <&k3_clks 240 1>; 669 clock-names = "fck"; 670 max-functions = /bits/ 8 <6>; 671 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 672 dma-coherent; 673 }; 674 675 pcie2_rc: pcie@2920000 { 676 compatible = "ti,j721e-pcie-host"; 677 reg = <0x00 0x02920000 0x00 0x1000>, 678 <0x00 0x02927000 0x00 0x400>, 679 <0x00 0x0e000000 0x00 0x00800000>, 680 <0x44 0x00000000 0x00 0x00001000>; 681 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 682 interrupt-names = "link_state"; 683 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 684 device_type = "pci"; 685 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 686 max-link-speed = <3>; 687 num-lanes = <2>; 688 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 689 clocks = <&k3_clks 241 1>; 690 clock-names = "fck"; 691 #address-cells = <3>; 692 #size-cells = <2>; 693 bus-range = <0x0 0xf>; 694 vendor-id = <0x104c>; 695 device-id = <0xb00d>; 696 msi-map = <0x0 &gic_its 0x20000 0x10000>; 697 dma-coherent; 698 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 699 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 700 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 701 }; 702 703 pcie2_ep: pcie-ep@2920000 { 704 compatible = "ti,j721e-pcie-ep"; 705 reg = <0x00 0x02920000 0x00 0x1000>, 706 <0x00 0x02927000 0x00 0x400>, 707 <0x00 0x0e000000 0x00 0x00800000>, 708 <0x44 0x00000000 0x00 0x08000000>; 709 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 710 interrupt-names = "link_state"; 711 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 712 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 713 max-link-speed = <3>; 714 num-lanes = <2>; 715 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 716 clocks = <&k3_clks 241 1>; 717 clock-names = "fck"; 718 max-functions = /bits/ 8 <6>; 719 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 720 dma-coherent; 721 }; 722 723 pcie3_rc: pcie@2930000 { 724 compatible = "ti,j721e-pcie-host"; 725 reg = <0x00 0x02930000 0x00 0x1000>, 726 <0x00 0x02937000 0x00 0x400>, 727 <0x00 0x0e800000 0x00 0x00800000>, 728 <0x44 0x10000000 0x00 0x00001000>; 729 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 730 interrupt-names = "link_state"; 731 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 732 device_type = "pci"; 733 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 734 max-link-speed = <3>; 735 num-lanes = <2>; 736 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 737 clocks = <&k3_clks 242 1>; 738 clock-names = "fck"; 739 #address-cells = <3>; 740 #size-cells = <2>; 741 bus-range = <0x0 0xf>; 742 vendor-id = <0x104c>; 743 device-id = <0xb00d>; 744 msi-map = <0x0 &gic_its 0x30000 0x10000>; 745 dma-coherent; 746 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 747 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 748 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 749 }; 750 751 pcie3_ep: pcie-ep@2930000 { 752 compatible = "ti,j721e-pcie-ep"; 753 reg = <0x00 0x02930000 0x00 0x1000>, 754 <0x00 0x02937000 0x00 0x400>, 755 <0x00 0x0e800000 0x00 0x00800000>, 756 <0x44 0x10000000 0x00 0x08000000>; 757 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 758 interrupt-names = "link_state"; 759 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 760 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 761 max-link-speed = <3>; 762 num-lanes = <2>; 763 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 764 clocks = <&k3_clks 242 1>; 765 clock-names = "fck"; 766 max-functions = /bits/ 8 <6>; 767 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 768 dma-coherent; 769 #address-cells = <2>; 770 #size-cells = <2>; 771 }; 772 773 main_uart0: serial@2800000 { 774 compatible = "ti,j721e-uart", "ti,am654-uart"; 775 reg = <0x00 0x02800000 0x00 0x100>; 776 reg-shift = <2>; 777 reg-io-width = <4>; 778 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 779 clock-frequency = <48000000>; 780 current-speed = <115200>; 781 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 782 clocks = <&k3_clks 146 0>; 783 clock-names = "fclk"; 784 }; 785 786 main_uart1: serial@2810000 { 787 compatible = "ti,j721e-uart", "ti,am654-uart"; 788 reg = <0x00 0x02810000 0x00 0x100>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 792 clock-frequency = <48000000>; 793 current-speed = <115200>; 794 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 795 clocks = <&k3_clks 278 0>; 796 clock-names = "fclk"; 797 }; 798 799 main_uart2: serial@2820000 { 800 compatible = "ti,j721e-uart", "ti,am654-uart"; 801 reg = <0x00 0x02820000 0x00 0x100>; 802 reg-shift = <2>; 803 reg-io-width = <4>; 804 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 805 clock-frequency = <48000000>; 806 current-speed = <115200>; 807 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 808 clocks = <&k3_clks 279 0>; 809 clock-names = "fclk"; 810 }; 811 812 main_uart3: serial@2830000 { 813 compatible = "ti,j721e-uart", "ti,am654-uart"; 814 reg = <0x00 0x02830000 0x00 0x100>; 815 reg-shift = <2>; 816 reg-io-width = <4>; 817 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 818 clock-frequency = <48000000>; 819 current-speed = <115200>; 820 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 821 clocks = <&k3_clks 280 0>; 822 clock-names = "fclk"; 823 }; 824 825 main_uart4: serial@2840000 { 826 compatible = "ti,j721e-uart", "ti,am654-uart"; 827 reg = <0x00 0x02840000 0x00 0x100>; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 831 clock-frequency = <48000000>; 832 current-speed = <115200>; 833 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 834 clocks = <&k3_clks 281 0>; 835 clock-names = "fclk"; 836 }; 837 838 main_uart5: serial@2850000 { 839 compatible = "ti,j721e-uart", "ti,am654-uart"; 840 reg = <0x00 0x02850000 0x00 0x100>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 844 clock-frequency = <48000000>; 845 current-speed = <115200>; 846 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 847 clocks = <&k3_clks 282 0>; 848 clock-names = "fclk"; 849 }; 850 851 main_uart6: serial@2860000 { 852 compatible = "ti,j721e-uart", "ti,am654-uart"; 853 reg = <0x00 0x02860000 0x00 0x100>; 854 reg-shift = <2>; 855 reg-io-width = <4>; 856 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 857 clock-frequency = <48000000>; 858 current-speed = <115200>; 859 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 860 clocks = <&k3_clks 283 0>; 861 clock-names = "fclk"; 862 }; 863 864 main_uart7: serial@2870000 { 865 compatible = "ti,j721e-uart", "ti,am654-uart"; 866 reg = <0x00 0x02870000 0x00 0x100>; 867 reg-shift = <2>; 868 reg-io-width = <4>; 869 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 870 clock-frequency = <48000000>; 871 current-speed = <115200>; 872 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 284 0>; 874 clock-names = "fclk"; 875 }; 876 877 main_uart8: serial@2880000 { 878 compatible = "ti,j721e-uart", "ti,am654-uart"; 879 reg = <0x00 0x02880000 0x00 0x100>; 880 reg-shift = <2>; 881 reg-io-width = <4>; 882 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 883 clock-frequency = <48000000>; 884 current-speed = <115200>; 885 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 886 clocks = <&k3_clks 285 0>; 887 clock-names = "fclk"; 888 }; 889 890 main_uart9: serial@2890000 { 891 compatible = "ti,j721e-uart", "ti,am654-uart"; 892 reg = <0x00 0x02890000 0x00 0x100>; 893 reg-shift = <2>; 894 reg-io-width = <4>; 895 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 896 clock-frequency = <48000000>; 897 current-speed = <115200>; 898 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 899 clocks = <&k3_clks 286 0>; 900 clock-names = "fclk"; 901 }; 902 903 main_gpio0: gpio@600000 { 904 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 905 reg = <0x0 0x00600000 0x0 0x100>; 906 gpio-controller; 907 #gpio-cells = <2>; 908 interrupt-parent = <&main_gpio_intr>; 909 interrupts = <256>, <257>, <258>, <259>, 910 <260>, <261>, <262>, <263>; 911 interrupt-controller; 912 #interrupt-cells = <2>; 913 ti,ngpio = <128>; 914 ti,davinci-gpio-unbanked = <0>; 915 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 916 clocks = <&k3_clks 105 0>; 917 clock-names = "gpio"; 918 }; 919 920 main_gpio1: gpio@601000 { 921 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 922 reg = <0x0 0x00601000 0x0 0x100>; 923 gpio-controller; 924 #gpio-cells = <2>; 925 interrupt-parent = <&main_gpio_intr>; 926 interrupts = <288>, <289>, <290>; 927 interrupt-controller; 928 #interrupt-cells = <2>; 929 ti,ngpio = <36>; 930 ti,davinci-gpio-unbanked = <0>; 931 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 932 clocks = <&k3_clks 106 0>; 933 clock-names = "gpio"; 934 }; 935 936 main_gpio2: gpio@610000 { 937 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 938 reg = <0x0 0x00610000 0x0 0x100>; 939 gpio-controller; 940 #gpio-cells = <2>; 941 interrupt-parent = <&main_gpio_intr>; 942 interrupts = <264>, <265>, <266>, <267>, 943 <268>, <269>, <270>, <271>; 944 interrupt-controller; 945 #interrupt-cells = <2>; 946 ti,ngpio = <128>; 947 ti,davinci-gpio-unbanked = <0>; 948 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 949 clocks = <&k3_clks 107 0>; 950 clock-names = "gpio"; 951 }; 952 953 main_gpio3: gpio@611000 { 954 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 955 reg = <0x0 0x00611000 0x0 0x100>; 956 gpio-controller; 957 #gpio-cells = <2>; 958 interrupt-parent = <&main_gpio_intr>; 959 interrupts = <292>, <293>, <294>; 960 interrupt-controller; 961 #interrupt-cells = <2>; 962 ti,ngpio = <36>; 963 ti,davinci-gpio-unbanked = <0>; 964 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 965 clocks = <&k3_clks 108 0>; 966 clock-names = "gpio"; 967 }; 968 969 main_gpio4: gpio@620000 { 970 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 971 reg = <0x0 0x00620000 0x0 0x100>; 972 gpio-controller; 973 #gpio-cells = <2>; 974 interrupt-parent = <&main_gpio_intr>; 975 interrupts = <272>, <273>, <274>, <275>, 976 <276>, <277>, <278>, <279>; 977 interrupt-controller; 978 #interrupt-cells = <2>; 979 ti,ngpio = <128>; 980 ti,davinci-gpio-unbanked = <0>; 981 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 982 clocks = <&k3_clks 109 0>; 983 clock-names = "gpio"; 984 }; 985 986 main_gpio5: gpio@621000 { 987 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 988 reg = <0x0 0x00621000 0x0 0x100>; 989 gpio-controller; 990 #gpio-cells = <2>; 991 interrupt-parent = <&main_gpio_intr>; 992 interrupts = <296>, <297>, <298>; 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 ti,ngpio = <36>; 996 ti,davinci-gpio-unbanked = <0>; 997 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 998 clocks = <&k3_clks 110 0>; 999 clock-names = "gpio"; 1000 }; 1001 1002 main_gpio6: gpio@630000 { 1003 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1004 reg = <0x0 0x00630000 0x0 0x100>; 1005 gpio-controller; 1006 #gpio-cells = <2>; 1007 interrupt-parent = <&main_gpio_intr>; 1008 interrupts = <280>, <281>, <282>, <283>, 1009 <284>, <285>, <286>, <287>; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 ti,ngpio = <128>; 1013 ti,davinci-gpio-unbanked = <0>; 1014 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1015 clocks = <&k3_clks 111 0>; 1016 clock-names = "gpio"; 1017 }; 1018 1019 main_gpio7: gpio@631000 { 1020 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1021 reg = <0x0 0x00631000 0x0 0x100>; 1022 gpio-controller; 1023 #gpio-cells = <2>; 1024 interrupt-parent = <&main_gpio_intr>; 1025 interrupts = <300>, <301>, <302>; 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 ti,ngpio = <36>; 1029 ti,davinci-gpio-unbanked = <0>; 1030 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1031 clocks = <&k3_clks 112 0>; 1032 clock-names = "gpio"; 1033 }; 1034 1035 main_sdhci0: mmc@4f80000 { 1036 compatible = "ti,j721e-sdhci-8bit"; 1037 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1038 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1039 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1040 clock-names = "clk_ahb", "clk_xin"; 1041 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1042 assigned-clocks = <&k3_clks 91 1>; 1043 assigned-clock-parents = <&k3_clks 91 2>; 1044 bus-width = <8>; 1045 mmc-hs400-1_8v; 1046 mmc-ddr-1_8v; 1047 ti,otap-del-sel-legacy = <0xf>; 1048 ti,otap-del-sel-mmc-hs = <0xf>; 1049 ti,otap-del-sel-ddr52 = <0x5>; 1050 ti,otap-del-sel-hs200 = <0x6>; 1051 ti,otap-del-sel-hs400 = <0x0>; 1052 ti,trm-icp = <0x8>; 1053 ti,strobe-sel = <0x77>; 1054 dma-coherent; 1055 }; 1056 1057 main_sdhci1: mmc@4fb0000 { 1058 compatible = "ti,j721e-sdhci-4bit"; 1059 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1060 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1062 clock-names = "clk_ahb", "clk_xin"; 1063 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1064 assigned-clocks = <&k3_clks 92 0>; 1065 assigned-clock-parents = <&k3_clks 92 1>; 1066 ti,otap-del-sel-legacy = <0x0>; 1067 ti,otap-del-sel-sd-hs = <0xf>; 1068 ti,otap-del-sel-sdr12 = <0xf>; 1069 ti,otap-del-sel-sdr25 = <0xf>; 1070 ti,otap-del-sel-sdr50 = <0xc>; 1071 ti,otap-del-sel-ddr50 = <0xc>; 1072 ti,trm-icp = <0x8>; 1073 ti,clkbuf-sel = <0x7>; 1074 dma-coherent; 1075 }; 1076 1077 main_sdhci2: mmc@4f98000 { 1078 compatible = "ti,j721e-sdhci-4bit"; 1079 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1080 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1081 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1082 clock-names = "clk_ahb", "clk_xin"; 1083 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1084 assigned-clocks = <&k3_clks 93 0>; 1085 assigned-clock-parents = <&k3_clks 93 1>; 1086 ti,otap-del-sel-legacy = <0x0>; 1087 ti,otap-del-sel-sd-hs = <0xf>; 1088 ti,otap-del-sel-sdr12 = <0xf>; 1089 ti,otap-del-sel-sdr25 = <0xf>; 1090 ti,otap-del-sel-sdr50 = <0xc>; 1091 ti,otap-del-sel-ddr50 = <0xc>; 1092 ti,trm-icp = <0x8>; 1093 ti,clkbuf-sel = <0x7>; 1094 dma-coherent; 1095 }; 1096 1097 usbss0: cdns-usb@4104000 { 1098 compatible = "ti,j721e-usb"; 1099 reg = <0x00 0x4104000 0x00 0x100>; 1100 dma-coherent; 1101 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1102 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1103 clock-names = "ref", "lpm"; 1104 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1105 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 1110 usb0: usb@6000000 { 1111 compatible = "cdns,usb3"; 1112 reg = <0x00 0x6000000 0x00 0x10000>, 1113 <0x00 0x6010000 0x00 0x10000>, 1114 <0x00 0x6020000 0x00 0x10000>; 1115 reg-names = "otg", "xhci", "dev"; 1116 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1117 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1118 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1119 interrupt-names = "host", 1120 "peripheral", 1121 "otg"; 1122 maximum-speed = "super-speed"; 1123 dr_mode = "otg"; 1124 }; 1125 }; 1126 1127 usbss1: cdns-usb@4114000 { 1128 compatible = "ti,j721e-usb"; 1129 reg = <0x00 0x4114000 0x00 0x100>; 1130 dma-coherent; 1131 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1132 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1133 clock-names = "ref", "lpm"; 1134 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1135 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1136 #address-cells = <2>; 1137 #size-cells = <2>; 1138 ranges; 1139 1140 usb1: usb@6400000 { 1141 compatible = "cdns,usb3"; 1142 reg = <0x00 0x6400000 0x00 0x10000>, 1143 <0x00 0x6410000 0x00 0x10000>, 1144 <0x00 0x6420000 0x00 0x10000>; 1145 reg-names = "otg", "xhci", "dev"; 1146 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1147 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1148 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1149 interrupt-names = "host", 1150 "peripheral", 1151 "otg"; 1152 maximum-speed = "super-speed"; 1153 dr_mode = "otg"; 1154 }; 1155 }; 1156 1157 main_i2c0: i2c@2000000 { 1158 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1159 reg = <0x0 0x2000000 0x0 0x100>; 1160 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 clock-names = "fck"; 1164 clocks = <&k3_clks 187 0>; 1165 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1166 }; 1167 1168 main_i2c1: i2c@2010000 { 1169 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1170 reg = <0x0 0x2010000 0x0 0x100>; 1171 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clock-names = "fck"; 1175 clocks = <&k3_clks 188 0>; 1176 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1177 }; 1178 1179 main_i2c2: i2c@2020000 { 1180 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1181 reg = <0x0 0x2020000 0x0 0x100>; 1182 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 clock-names = "fck"; 1186 clocks = <&k3_clks 189 0>; 1187 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1188 }; 1189 1190 main_i2c3: i2c@2030000 { 1191 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1192 reg = <0x0 0x2030000 0x0 0x100>; 1193 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 clock-names = "fck"; 1197 clocks = <&k3_clks 190 0>; 1198 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1199 }; 1200 1201 main_i2c4: i2c@2040000 { 1202 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1203 reg = <0x0 0x2040000 0x0 0x100>; 1204 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 clock-names = "fck"; 1208 clocks = <&k3_clks 191 0>; 1209 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1210 }; 1211 1212 main_i2c5: i2c@2050000 { 1213 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1214 reg = <0x0 0x2050000 0x0 0x100>; 1215 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 clock-names = "fck"; 1219 clocks = <&k3_clks 192 0>; 1220 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1221 }; 1222 1223 main_i2c6: i2c@2060000 { 1224 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1225 reg = <0x0 0x2060000 0x0 0x100>; 1226 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 clock-names = "fck"; 1230 clocks = <&k3_clks 193 0>; 1231 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1232 }; 1233 1234 ufs_wrapper: ufs-wrapper@4e80000 { 1235 compatible = "ti,j721e-ufs"; 1236 reg = <0x0 0x4e80000 0x0 0x100>; 1237 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1238 clocks = <&k3_clks 277 1>; 1239 assigned-clocks = <&k3_clks 277 1>; 1240 assigned-clock-parents = <&k3_clks 277 4>; 1241 ranges; 1242 #address-cells = <2>; 1243 #size-cells = <2>; 1244 1245 ufs@4e84000 { 1246 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1247 reg = <0x0 0x4e84000 0x0 0x10000>; 1248 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1249 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1250 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1251 clock-names = "core_clk", "phy_clk", "ref_clk"; 1252 dma-coherent; 1253 }; 1254 }; 1255 1256 dss: dss@4a00000 { 1257 compatible = "ti,j721e-dss"; 1258 reg = 1259 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1260 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1261 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1262 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1263 1264 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1265 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1266 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1267 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1268 1269 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1270 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1271 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1272 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1273 1274 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1275 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1276 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1277 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1278 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1279 1280 reg-names = "common_m", "common_s0", 1281 "common_s1", "common_s2", 1282 "vidl1", "vidl2","vid1","vid2", 1283 "ovr1", "ovr2", "ovr3", "ovr4", 1284 "vp1", "vp2", "vp3", "vp4", 1285 "wb"; 1286 1287 clocks = <&k3_clks 152 0>, 1288 <&k3_clks 152 1>, 1289 <&k3_clks 152 4>, 1290 <&k3_clks 152 9>, 1291 <&k3_clks 152 13>; 1292 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1293 1294 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1295 1296 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1300 interrupt-names = "common_m", 1301 "common_s0", 1302 "common_s1", 1303 "common_s2"; 1304 1305 dss_ports: ports { 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 }; 1309 }; 1310 1311 mcasp0: mcasp@2b00000 { 1312 compatible = "ti,am33xx-mcasp-audio"; 1313 reg = <0x0 0x02b00000 0x0 0x2000>, 1314 <0x0 0x02b08000 0x0 0x1000>; 1315 reg-names = "mpu","dat"; 1316 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1318 interrupt-names = "tx", "rx"; 1319 1320 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1321 dma-names = "tx", "rx"; 1322 1323 clocks = <&k3_clks 174 1>; 1324 clock-names = "fck"; 1325 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1326 }; 1327 1328 mcasp1: mcasp@2b10000 { 1329 compatible = "ti,am33xx-mcasp-audio"; 1330 reg = <0x0 0x02b10000 0x0 0x2000>, 1331 <0x0 0x02b18000 0x0 0x1000>; 1332 reg-names = "mpu","dat"; 1333 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1335 interrupt-names = "tx", "rx"; 1336 1337 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1338 dma-names = "tx", "rx"; 1339 1340 clocks = <&k3_clks 175 1>; 1341 clock-names = "fck"; 1342 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1343 }; 1344 1345 mcasp2: mcasp@2b20000 { 1346 compatible = "ti,am33xx-mcasp-audio"; 1347 reg = <0x0 0x02b20000 0x0 0x2000>, 1348 <0x0 0x02b28000 0x0 0x1000>; 1349 reg-names = "mpu","dat"; 1350 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1352 interrupt-names = "tx", "rx"; 1353 1354 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1355 dma-names = "tx", "rx"; 1356 1357 clocks = <&k3_clks 176 1>; 1358 clock-names = "fck"; 1359 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1360 }; 1361 1362 mcasp3: mcasp@2b30000 { 1363 compatible = "ti,am33xx-mcasp-audio"; 1364 reg = <0x0 0x02b30000 0x0 0x2000>, 1365 <0x0 0x02b38000 0x0 0x1000>; 1366 reg-names = "mpu","dat"; 1367 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1369 interrupt-names = "tx", "rx"; 1370 1371 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1372 dma-names = "tx", "rx"; 1373 1374 clocks = <&k3_clks 177 1>; 1375 clock-names = "fck"; 1376 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1377 }; 1378 1379 mcasp4: mcasp@2b40000 { 1380 compatible = "ti,am33xx-mcasp-audio"; 1381 reg = <0x0 0x02b40000 0x0 0x2000>, 1382 <0x0 0x02b48000 0x0 0x1000>; 1383 reg-names = "mpu","dat"; 1384 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "tx", "rx"; 1387 1388 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1389 dma-names = "tx", "rx"; 1390 1391 clocks = <&k3_clks 178 1>; 1392 clock-names = "fck"; 1393 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1394 }; 1395 1396 mcasp5: mcasp@2b50000 { 1397 compatible = "ti,am33xx-mcasp-audio"; 1398 reg = <0x0 0x02b50000 0x0 0x2000>, 1399 <0x0 0x02b58000 0x0 0x1000>; 1400 reg-names = "mpu","dat"; 1401 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "tx", "rx"; 1404 1405 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1406 dma-names = "tx", "rx"; 1407 1408 clocks = <&k3_clks 179 1>; 1409 clock-names = "fck"; 1410 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1411 }; 1412 1413 mcasp6: mcasp@2b60000 { 1414 compatible = "ti,am33xx-mcasp-audio"; 1415 reg = <0x0 0x02b60000 0x0 0x2000>, 1416 <0x0 0x02b68000 0x0 0x1000>; 1417 reg-names = "mpu","dat"; 1418 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1420 interrupt-names = "tx", "rx"; 1421 1422 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1423 dma-names = "tx", "rx"; 1424 1425 clocks = <&k3_clks 180 1>; 1426 clock-names = "fck"; 1427 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1428 }; 1429 1430 mcasp7: mcasp@2b70000 { 1431 compatible = "ti,am33xx-mcasp-audio"; 1432 reg = <0x0 0x02b70000 0x0 0x2000>, 1433 <0x0 0x02b78000 0x0 0x1000>; 1434 reg-names = "mpu","dat"; 1435 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1437 interrupt-names = "tx", "rx"; 1438 1439 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1440 dma-names = "tx", "rx"; 1441 1442 clocks = <&k3_clks 181 1>; 1443 clock-names = "fck"; 1444 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1445 }; 1446 1447 mcasp8: mcasp@2b80000 { 1448 compatible = "ti,am33xx-mcasp-audio"; 1449 reg = <0x0 0x02b80000 0x0 0x2000>, 1450 <0x0 0x02b88000 0x0 0x1000>; 1451 reg-names = "mpu","dat"; 1452 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1454 interrupt-names = "tx", "rx"; 1455 1456 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1457 dma-names = "tx", "rx"; 1458 1459 clocks = <&k3_clks 182 1>; 1460 clock-names = "fck"; 1461 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1462 }; 1463 1464 mcasp9: mcasp@2b90000 { 1465 compatible = "ti,am33xx-mcasp-audio"; 1466 reg = <0x0 0x02b90000 0x0 0x2000>, 1467 <0x0 0x02b98000 0x0 0x1000>; 1468 reg-names = "mpu","dat"; 1469 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1471 interrupt-names = "tx", "rx"; 1472 1473 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1474 dma-names = "tx", "rx"; 1475 1476 clocks = <&k3_clks 183 1>; 1477 clock-names = "fck"; 1478 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1479 }; 1480 1481 mcasp10: mcasp@2ba0000 { 1482 compatible = "ti,am33xx-mcasp-audio"; 1483 reg = <0x0 0x02ba0000 0x0 0x2000>, 1484 <0x0 0x02ba8000 0x0 0x1000>; 1485 reg-names = "mpu","dat"; 1486 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1488 interrupt-names = "tx", "rx"; 1489 1490 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1491 dma-names = "tx", "rx"; 1492 1493 clocks = <&k3_clks 184 1>; 1494 clock-names = "fck"; 1495 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1496 }; 1497 1498 mcasp11: mcasp@2bb0000 { 1499 compatible = "ti,am33xx-mcasp-audio"; 1500 reg = <0x0 0x02bb0000 0x0 0x2000>, 1501 <0x0 0x02bb8000 0x0 0x1000>; 1502 reg-names = "mpu","dat"; 1503 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1505 interrupt-names = "tx", "rx"; 1506 1507 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1508 dma-names = "tx", "rx"; 1509 1510 clocks = <&k3_clks 185 1>; 1511 clock-names = "fck"; 1512 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1513 }; 1514 1515 watchdog0: watchdog@2200000 { 1516 compatible = "ti,j7-rti-wdt"; 1517 reg = <0x0 0x2200000 0x0 0x100>; 1518 clocks = <&k3_clks 252 1>; 1519 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1520 assigned-clocks = <&k3_clks 252 1>; 1521 assigned-clock-parents = <&k3_clks 252 5>; 1522 }; 1523 1524 watchdog1: watchdog@2210000 { 1525 compatible = "ti,j7-rti-wdt"; 1526 reg = <0x0 0x2210000 0x0 0x100>; 1527 clocks = <&k3_clks 253 1>; 1528 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1529 assigned-clocks = <&k3_clks 253 1>; 1530 assigned-clock-parents = <&k3_clks 253 5>; 1531 }; 1532 1533 main_r5fss0: r5fss@5c00000 { 1534 compatible = "ti,j721e-r5fss"; 1535 ti,cluster-mode = <1>; 1536 #address-cells = <1>; 1537 #size-cells = <1>; 1538 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1539 <0x5d00000 0x00 0x5d00000 0x20000>; 1540 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1541 1542 main_r5fss0_core0: r5f@5c00000 { 1543 compatible = "ti,j721e-r5f"; 1544 reg = <0x5c00000 0x00008000>, 1545 <0x5c10000 0x00008000>; 1546 reg-names = "atcm", "btcm"; 1547 ti,sci = <&dmsc>; 1548 ti,sci-dev-id = <245>; 1549 ti,sci-proc-ids = <0x06 0xff>; 1550 resets = <&k3_reset 245 1>; 1551 firmware-name = "j7-main-r5f0_0-fw"; 1552 ti,atcm-enable = <1>; 1553 ti,btcm-enable = <1>; 1554 ti,loczrama = <1>; 1555 }; 1556 1557 main_r5fss0_core1: r5f@5d00000 { 1558 compatible = "ti,j721e-r5f"; 1559 reg = <0x5d00000 0x00008000>, 1560 <0x5d10000 0x00008000>; 1561 reg-names = "atcm", "btcm"; 1562 ti,sci = <&dmsc>; 1563 ti,sci-dev-id = <246>; 1564 ti,sci-proc-ids = <0x07 0xff>; 1565 resets = <&k3_reset 246 1>; 1566 firmware-name = "j7-main-r5f0_1-fw"; 1567 ti,atcm-enable = <1>; 1568 ti,btcm-enable = <1>; 1569 ti,loczrama = <1>; 1570 }; 1571 }; 1572 1573 main_r5fss1: r5fss@5e00000 { 1574 compatible = "ti,j721e-r5fss"; 1575 ti,cluster-mode = <1>; 1576 #address-cells = <1>; 1577 #size-cells = <1>; 1578 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1579 <0x5f00000 0x00 0x5f00000 0x20000>; 1580 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1581 1582 main_r5fss1_core0: r5f@5e00000 { 1583 compatible = "ti,j721e-r5f"; 1584 reg = <0x5e00000 0x00008000>, 1585 <0x5e10000 0x00008000>; 1586 reg-names = "atcm", "btcm"; 1587 ti,sci = <&dmsc>; 1588 ti,sci-dev-id = <247>; 1589 ti,sci-proc-ids = <0x08 0xff>; 1590 resets = <&k3_reset 247 1>; 1591 firmware-name = "j7-main-r5f1_0-fw"; 1592 ti,atcm-enable = <1>; 1593 ti,btcm-enable = <1>; 1594 ti,loczrama = <1>; 1595 }; 1596 1597 main_r5fss1_core1: r5f@5f00000 { 1598 compatible = "ti,j721e-r5f"; 1599 reg = <0x5f00000 0x00008000>, 1600 <0x5f10000 0x00008000>; 1601 reg-names = "atcm", "btcm"; 1602 ti,sci = <&dmsc>; 1603 ti,sci-dev-id = <248>; 1604 ti,sci-proc-ids = <0x09 0xff>; 1605 resets = <&k3_reset 248 1>; 1606 firmware-name = "j7-main-r5f1_1-fw"; 1607 ti,atcm-enable = <1>; 1608 ti,btcm-enable = <1>; 1609 ti,loczrama = <1>; 1610 }; 1611 }; 1612 1613 c66_0: dsp@4d80800000 { 1614 compatible = "ti,j721e-c66-dsp"; 1615 reg = <0x4d 0x80800000 0x00 0x00048000>, 1616 <0x4d 0x80e00000 0x00 0x00008000>, 1617 <0x4d 0x80f00000 0x00 0x00008000>; 1618 reg-names = "l2sram", "l1pram", "l1dram"; 1619 ti,sci = <&dmsc>; 1620 ti,sci-dev-id = <142>; 1621 ti,sci-proc-ids = <0x03 0xff>; 1622 resets = <&k3_reset 142 1>; 1623 firmware-name = "j7-c66_0-fw"; 1624 }; 1625 1626 c66_1: dsp@4d81800000 { 1627 compatible = "ti,j721e-c66-dsp"; 1628 reg = <0x4d 0x81800000 0x00 0x00048000>, 1629 <0x4d 0x81e00000 0x00 0x00008000>, 1630 <0x4d 0x81f00000 0x00 0x00008000>; 1631 reg-names = "l2sram", "l1pram", "l1dram"; 1632 ti,sci = <&dmsc>; 1633 ti,sci-dev-id = <143>; 1634 ti,sci-proc-ids = <0x04 0xff>; 1635 resets = <&k3_reset 143 1>; 1636 firmware-name = "j7-c66_1-fw"; 1637 }; 1638 1639 c71_0: dsp@64800000 { 1640 compatible = "ti,j721e-c71-dsp"; 1641 reg = <0x00 0x64800000 0x00 0x00080000>, 1642 <0x00 0x64e00000 0x00 0x0000c000>; 1643 reg-names = "l2sram", "l1dram"; 1644 ti,sci = <&dmsc>; 1645 ti,sci-dev-id = <15>; 1646 ti,sci-proc-ids = <0x30 0xff>; 1647 resets = <&k3_reset 15 1>; 1648 firmware-name = "j7-c71_0-fw"; 1649 }; 1650}; 1651