1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/net/ti-dp83867.h> 12 13/ { 14 chosen { 15 stdout-path = "serial2:115200n8"; 16 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 17 }; 18 19 gpio_keys: gpio-keys { 20 compatible = "gpio-keys"; 21 autorepeat; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; 24 25 sw10: sw10 { 26 label = "GPIO Key USER1"; 27 linux,code = <BTN_0>; 28 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 29 }; 30 31 sw11: sw11 { 32 label = "GPIO Key USER2"; 33 linux,code = <BTN_1>; 34 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 35 }; 36 }; 37 38 evm_12v0: fixedregulator-evm12v0 { 39 /* main supply */ 40 compatible = "regulator-fixed"; 41 regulator-name = "evm_12v0"; 42 regulator-min-microvolt = <12000000>; 43 regulator-max-microvolt = <12000000>; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 vsys_3v3: fixedregulator-vsys3v3 { 49 /* Output of LMS140 */ 50 compatible = "regulator-fixed"; 51 regulator-name = "vsys_3v3"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&evm_12v0>; 55 regulator-always-on; 56 regulator-boot-on; 57 }; 58 59 vsys_5v0: fixedregulator-vsys5v0 { 60 /* Output of LM5140 */ 61 compatible = "regulator-fixed"; 62 regulator-name = "vsys_5v0"; 63 regulator-min-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>; 65 vin-supply = <&evm_12v0>; 66 regulator-always-on; 67 regulator-boot-on; 68 }; 69 70 vdd_mmc1: fixedregulator-sd { 71 compatible = "regulator-fixed"; 72 regulator-name = "vdd_mmc1"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-boot-on; 76 enable-active-high; 77 vin-supply = <&vsys_3v3>; 78 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 79 }; 80 81 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 82 compatible = "regulator-gpio"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 85 regulator-name = "tlv71033"; 86 regulator-min-microvolt = <1800000>; 87 regulator-max-microvolt = <3300000>; 88 regulator-boot-on; 89 vin-supply = <&vsys_5v0>; 90 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 91 states = <1800000 0x0>, 92 <3300000 0x1>; 93 }; 94 95 sound0: sound@0 { 96 compatible = "ti,j721e-cpb-audio"; 97 model = "j721e-cpb"; 98 99 ti,cpb-mcasp = <&mcasp10>; 100 ti,cpb-codec = <&pcm3168a_1>; 101 102 clocks = <&k3_clks 184 1>, 103 <&k3_clks 184 2>, <&k3_clks 184 4>, 104 <&k3_clks 157 371>, 105 <&k3_clks 157 400>, <&k3_clks 157 401>; 106 clock-names = "cpb-mcasp-auxclk", 107 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 108 "cpb-codec-scki", 109 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 110 }; 111}; 112 113&main_pmx0 { 114 sw10_button_pins_default: sw10-button-pins-default { 115 pinctrl-single,pins = < 116 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 117 >; 118 }; 119 120 main_mmc1_pins_default: main-mmc1-pins-default { 121 pinctrl-single,pins = < 122 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 123 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 124 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 125 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 126 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 127 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 128 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 129 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 130 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 131 >; 132 }; 133 134 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 135 pinctrl-single,pins = < 136 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 137 >; 138 }; 139 140 main_usbss0_pins_default: main-usbss0-pins-default { 141 pinctrl-single,pins = < 142 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 143 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 144 >; 145 }; 146 147 main_usbss1_pins_default: main-usbss1-pins-default { 148 pinctrl-single,pins = < 149 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 150 >; 151 }; 152 153 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { 154 pinctrl-single,pins = < 155 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 156 >; 157 }; 158 159 main_i2c0_pins_default: main-i2c0-pins-default { 160 pinctrl-single,pins = < 161 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 162 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 163 >; 164 }; 165 166 main_i2c1_pins_default: main-i2c1-pins-default { 167 pinctrl-single,pins = < 168 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 169 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 170 >; 171 }; 172 173 main_i2c3_pins_default: main-i2c3-pins-default { 174 pinctrl-single,pins = < 175 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 176 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 177 >; 178 }; 179 180 main_i2c6_pins_default: main-i2c6-pins-default { 181 pinctrl-single,pins = < 182 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 183 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 184 >; 185 }; 186 187 mcasp10_pins_default: mcasp10-pins-default { 188 pinctrl-single,pins = < 189 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 190 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 191 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 192 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 193 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 194 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 195 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 196 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 197 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 198 >; 199 }; 200 201 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { 202 pinctrl-single,pins = < 203 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 204 >; 205 }; 206}; 207 208&wkup_pmx0 { 209 sw11_button_pins_default: sw11-button-pins-default { 210 pinctrl-single,pins = < 211 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 212 >; 213 }; 214 215 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 216 pinctrl-single,pins = < 217 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 218 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 219 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 220 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 221 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 222 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 223 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 224 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 225 >; 226 }; 227 228 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 229 pinctrl-single,pins = < 230 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 231 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 232 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 233 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 234 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 235 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 236 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 237 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 238 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 239 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 240 J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ 241 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 242 >; 243 }; 244 245 mcu_mdio_pins_default: mcu-mdio1-pins-default { 246 pinctrl-single,pins = < 247 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 248 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 249 >; 250 }; 251}; 252 253&wkup_uart0 { 254 /* Wakeup UART is used by System firmware */ 255 status = "reserved"; 256}; 257 258&main_uart0 { 259 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 260}; 261 262&main_uart3 { 263 /* UART not brought out */ 264 status = "disabled"; 265}; 266 267&main_uart5 { 268 /* UART not brought out */ 269 status = "disabled"; 270}; 271 272&main_uart6 { 273 /* UART not brought out */ 274 status = "disabled"; 275}; 276 277&main_uart7 { 278 /* UART not brought out */ 279 status = "disabled"; 280}; 281 282&main_uart8 { 283 /* UART not brought out */ 284 status = "disabled"; 285}; 286 287&main_uart9 { 288 /* UART not brought out */ 289 status = "disabled"; 290}; 291 292&main_gpio2 { 293 status = "disabled"; 294}; 295 296&main_gpio3 { 297 status = "disabled"; 298}; 299 300&main_gpio4 { 301 status = "disabled"; 302}; 303 304&main_gpio5 { 305 status = "disabled"; 306}; 307 308&main_gpio6 { 309 status = "disabled"; 310}; 311 312&main_gpio7 { 313 status = "disabled"; 314}; 315 316&wkup_gpio1 { 317 status = "disabled"; 318}; 319 320&main_sdhci0 { 321 /* eMMC */ 322 non-removable; 323 ti,driver-strength-ohm = <50>; 324 disable-wp; 325}; 326 327&main_sdhci1 { 328 /* SD/MMC */ 329 vmmc-supply = <&vdd_mmc1>; 330 vqmmc-supply = <&vdd_sd_dv_alt>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&main_mmc1_pins_default>; 333 ti,driver-strength-ohm = <50>; 334 disable-wp; 335}; 336 337&main_sdhci2 { 338 /* Unused */ 339 status = "disabled"; 340}; 341 342&usb_serdes_mux { 343 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 344}; 345 346&serdes_ln_ctrl { 347 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 348 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 349 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 350 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 351 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 352 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 353}; 354 355&serdes_wiz3 { 356 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 357 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 358}; 359 360&serdes3 { 361 serdes3_usb_link: link@0 { 362 reg = <0>; 363 cdns,num-lanes = <2>; 364 #phy-cells = <0>; 365 cdns,phy-type = <PHY_TYPE_USB3>; 366 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 367 }; 368}; 369 370&usbss0 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&main_usbss0_pins_default>; 373 ti,vbus-divider; 374}; 375 376&usb0 { 377 dr_mode = "otg"; 378 maximum-speed = "super-speed"; 379 phys = <&serdes3_usb_link>; 380 phy-names = "cdns3,usb3-phy"; 381}; 382 383&usbss1 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&main_usbss1_pins_default>; 386 ti,usb2-only; 387}; 388 389&usb1 { 390 dr_mode = "host"; 391 maximum-speed = "high-speed"; 392}; 393 394&ospi1 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 397 398 flash@0{ 399 compatible = "jedec,spi-nor"; 400 reg = <0x0>; 401 spi-tx-bus-width = <1>; 402 spi-rx-bus-width = <4>; 403 spi-max-frequency = <40000000>; 404 cdns,tshsl-ns = <60>; 405 cdns,tsd2d-ns = <60>; 406 cdns,tchsh-ns = <60>; 407 cdns,tslch-ns = <60>; 408 cdns,read-delay = <2>; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 }; 412}; 413 414&tscadc0 { 415 adc { 416 ti,adc-channels = <0 1 2 3 4 5 6 7>; 417 }; 418}; 419 420&tscadc1 { 421 adc { 422 ti,adc-channels = <0 1 2 3 4 5 6 7>; 423 }; 424}; 425 426&main_i2c0 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&main_i2c0_pins_default>; 429 clock-frequency = <400000>; 430 431 exp1: gpio@20 { 432 compatible = "ti,tca6416"; 433 reg = <0x20>; 434 gpio-controller; 435 #gpio-cells = <2>; 436 }; 437 438 exp2: gpio@22 { 439 compatible = "ti,tca6424"; 440 reg = <0x22>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 444 p09-hog { 445 /* P11 - MCASP/TRACE_MUX_S0 */ 446 gpio-hog; 447 gpios = <9 GPIO_ACTIVE_HIGH>; 448 output-low; 449 line-name = "MCASP/TRACE_MUX_S0"; 450 }; 451 452 p10-hog { 453 /* P12 - MCASP/TRACE_MUX_S1 */ 454 gpio-hog; 455 gpios = <10 GPIO_ACTIVE_HIGH>; 456 output-high; 457 line-name = "MCASP/TRACE_MUX_S1"; 458 }; 459 }; 460}; 461 462&main_i2c1 { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&main_i2c1_pins_default>; 465 clock-frequency = <400000>; 466 467 exp4: gpio@20 { 468 compatible = "ti,tca6408"; 469 reg = <0x20>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 474 interrupt-parent = <&main_gpio1>; 475 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 }; 479}; 480 481&k3_clks { 482 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 483 pinctrl-names = "default"; 484 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 485}; 486 487&main_i2c3 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&main_i2c3_pins_default>; 490 clock-frequency = <400000>; 491 492 exp3: gpio@20 { 493 compatible = "ti,tca6408"; 494 reg = <0x20>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 }; 498 499 pcm3168a_1: audio-codec@44 { 500 compatible = "ti,pcm3168a"; 501 reg = <0x44>; 502 503 #sound-dai-cells = <1>; 504 505 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 506 507 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 508 clocks = <&k3_clks 157 371>; 509 clock-names = "scki"; 510 511 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 512 assigned-clocks = <&k3_clks 157 371>; 513 assigned-clock-parents = <&k3_clks 157 400>; 514 assigned-clock-rates = <24576000>; /* for 48KHz */ 515 516 VDD1-supply = <&vsys_3v3>; 517 VDD2-supply = <&vsys_3v3>; 518 VCCAD1-supply = <&vsys_5v0>; 519 VCCAD2-supply = <&vsys_5v0>; 520 VCCDA1-supply = <&vsys_5v0>; 521 VCCDA2-supply = <&vsys_5v0>; 522 }; 523}; 524 525&main_i2c6 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&main_i2c6_pins_default>; 528 clock-frequency = <400000>; 529 530 exp5: gpio@20 { 531 compatible = "ti,tca6408"; 532 reg = <0x20>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 }; 536}; 537 538&mcu_cpsw { 539 pinctrl-names = "default"; 540 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 541}; 542 543&davinci_mdio { 544 phy0: ethernet-phy@0 { 545 reg = <0>; 546 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 547 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 548 }; 549}; 550 551&cpsw_port1 { 552 phy-mode = "rgmii-rxid"; 553 phy-handle = <&phy0>; 554}; 555 556&dss { 557 /* 558 * These clock assignments are chosen to enable the following outputs: 559 * 560 * VP0 - DisplayPort SST 561 * VP1 - DPI0 562 * VP2 - DSI 563 * VP3 - DPI1 564 */ 565 566 assigned-clocks = <&k3_clks 152 1>, 567 <&k3_clks 152 4>, 568 <&k3_clks 152 9>, 569 <&k3_clks 152 13>; 570 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 571 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 572 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 573 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 574}; 575 576&mcasp0 { 577 status = "disabled"; 578}; 579 580&mcasp1 { 581 status = "disabled"; 582}; 583 584&mcasp2 { 585 status = "disabled"; 586}; 587 588&mcasp3 { 589 status = "disabled"; 590}; 591 592&mcasp4 { 593 status = "disabled"; 594}; 595 596&mcasp5 { 597 status = "disabled"; 598}; 599 600&mcasp6 { 601 status = "disabled"; 602}; 603 604&mcasp7 { 605 status = "disabled"; 606}; 607 608&mcasp8 { 609 status = "disabled"; 610}; 611 612&mcasp9 { 613 status = "disabled"; 614}; 615 616&mcasp10 { 617 #sound-dai-cells = <0>; 618 619 pinctrl-names = "default"; 620 pinctrl-0 = <&mcasp10_pins_default>; 621 622 op-mode = <0>; /* MCASP_IIS_MODE */ 623 tdm-slots = <2>; 624 auxclk-fs-ratio = <256>; 625 626 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 627 1 1 1 1 628 2 2 2 0 629 >; 630 tx-num-evt = <0>; 631 rx-num-evt = <0>; 632}; 633 634&mcasp11 { 635 status = "disabled"; 636}; 637 638&serdes0 { 639 serdes0_pcie_link: link@0 { 640 reg = <0>; 641 cdns,num-lanes = <1>; 642 #phy-cells = <0>; 643 cdns,phy-type = <PHY_TYPE_PCIE>; 644 resets = <&serdes_wiz0 1>; 645 }; 646}; 647 648&serdes1 { 649 serdes1_pcie_link: link@0 { 650 reg = <0>; 651 cdns,num-lanes = <2>; 652 #phy-cells = <0>; 653 cdns,phy-type = <PHY_TYPE_PCIE>; 654 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 655 }; 656}; 657 658&serdes2 { 659 serdes2_pcie_link: link@0 { 660 reg = <0>; 661 cdns,num-lanes = <2>; 662 #phy-cells = <0>; 663 cdns,phy-type = <PHY_TYPE_PCIE>; 664 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 665 }; 666}; 667 668&pcie0_rc { 669 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 670 phys = <&serdes0_pcie_link>; 671 phy-names = "pcie-phy"; 672 num-lanes = <1>; 673}; 674 675&pcie1_rc { 676 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 677 phys = <&serdes1_pcie_link>; 678 phy-names = "pcie-phy"; 679 num-lanes = <2>; 680}; 681 682&pcie2_rc { 683 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 684 phys = <&serdes2_pcie_link>; 685 phy-names = "pcie-phy"; 686 num-lanes = <2>; 687}; 688 689&pcie0_ep { 690 phys = <&serdes0_pcie_link>; 691 phy-names = "pcie-phy"; 692 num-lanes = <1>; 693 status = "disabled"; 694}; 695 696&pcie1_ep { 697 phys = <&serdes1_pcie_link>; 698 phy-names = "pcie-phy"; 699 num-lanes = <2>; 700 status = "disabled"; 701}; 702 703&pcie2_ep { 704 phys = <&serdes2_pcie_link>; 705 phy-names = "pcie-phy"; 706 num-lanes = <2>; 707 status = "disabled"; 708}; 709 710&pcie3_rc { 711 status = "disabled"; 712}; 713 714&pcie3_ep { 715 status = "disabled"; 716}; 717 718&dss { 719 status = "disabled"; 720}; 721