xref: /freebsd/sys/contrib/device-tree/src/arm64/ti/k3-j721e-common-proc-board.dts (revision c7046f76c2c027b00c0e6ba57cfd28f1a78f5e23)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721e-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy-cadence.h>
13
14/ {
15	compatible = "ti,j721e-evm", "ti,j721e";
16	model = "Texas Instruments J721e EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	gpio_keys: gpio-keys {
24		compatible = "gpio-keys";
25		autorepeat;
26		pinctrl-names = "default";
27		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
28
29		sw10: sw10 {
30			label = "GPIO Key USER1";
31			linux,code = <BTN_0>;
32			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
33		};
34
35		sw11: sw11 {
36			label = "GPIO Key USER2";
37			linux,code = <BTN_1>;
38			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
39		};
40	};
41
42	evm_12v0: fixedregulator-evm12v0 {
43		/* main supply */
44		compatible = "regulator-fixed";
45		regulator-name = "evm_12v0";
46		regulator-min-microvolt = <12000000>;
47		regulator-max-microvolt = <12000000>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	vsys_3v3: fixedregulator-vsys3v3 {
53		/* Output of LMS140 */
54		compatible = "regulator-fixed";
55		regulator-name = "vsys_3v3";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		vin-supply = <&evm_12v0>;
59		regulator-always-on;
60		regulator-boot-on;
61	};
62
63	vsys_5v0: fixedregulator-vsys5v0 {
64		/* Output of LM5140 */
65		compatible = "regulator-fixed";
66		regulator-name = "vsys_5v0";
67		regulator-min-microvolt = <5000000>;
68		regulator-max-microvolt = <5000000>;
69		vin-supply = <&evm_12v0>;
70		regulator-always-on;
71		regulator-boot-on;
72	};
73
74	vdd_mmc1: fixedregulator-sd {
75		compatible = "regulator-fixed";
76		regulator-name = "vdd_mmc1";
77		regulator-min-microvolt = <3300000>;
78		regulator-max-microvolt = <3300000>;
79		regulator-boot-on;
80		enable-active-high;
81		vin-supply = <&vsys_3v3>;
82		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
83	};
84
85	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
86		compatible = "regulator-gpio";
87		pinctrl-names = "default";
88		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
89		regulator-name = "tlv71033";
90		regulator-min-microvolt = <1800000>;
91		regulator-max-microvolt = <3300000>;
92		regulator-boot-on;
93		vin-supply = <&vsys_5v0>;
94		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
95		states = <1800000 0x0>,
96			 <3300000 0x1>;
97	};
98
99	sound0: sound@0 {
100		compatible = "ti,j721e-cpb-audio";
101		model = "j721e-cpb";
102
103		ti,cpb-mcasp = <&mcasp10>;
104		ti,cpb-codec = <&pcm3168a_1>;
105
106		clocks = <&k3_clks 184 1>,
107			 <&k3_clks 184 2>, <&k3_clks 184 4>,
108			 <&k3_clks 157 371>,
109			 <&k3_clks 157 400>, <&k3_clks 157 401>;
110		clock-names = "cpb-mcasp-auxclk",
111			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
112			      "cpb-codec-scki",
113			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
114	};
115
116	transceiver1: can-phy0 {
117		compatible = "ti,tcan1043";
118		#phy-cells = <0>;
119		max-bitrate = <5000000>;
120		pinctrl-names = "default";
121		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
122		standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
123		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
124	};
125
126	transceiver2: can-phy1 {
127		compatible = "ti,tcan1042";
128		#phy-cells = <0>;
129		max-bitrate = <5000000>;
130		pinctrl-names = "default";
131		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
132		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
133	};
134
135	transceiver3: can-phy2 {
136		compatible = "ti,tcan1043";
137		#phy-cells = <0>;
138		max-bitrate = <5000000>;
139		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
140		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
141	};
142
143	transceiver4: can-phy3 {
144		compatible = "ti,tcan1042";
145		#phy-cells = <0>;
146		max-bitrate = <5000000>;
147		pinctrl-names = "default";
148		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
149		standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
150	};
151};
152
153&main_pmx0 {
154	sw10_button_pins_default: sw10-button-pins-default {
155		pinctrl-single,pins = <
156			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
157		>;
158	};
159
160	main_mmc1_pins_default: main-mmc1-pins-default {
161		pinctrl-single,pins = <
162			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
163			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
164			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
165			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
166			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
167			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
168			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
169			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
170			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
171		>;
172	};
173
174	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
175		pinctrl-single,pins = <
176			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
177		>;
178	};
179
180	main_usbss0_pins_default: main-usbss0-pins-default {
181		pinctrl-single,pins = <
182			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
183			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
184		>;
185	};
186
187	main_usbss1_pins_default: main-usbss1-pins-default {
188		pinctrl-single,pins = <
189			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
190		>;
191	};
192
193	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
194		pinctrl-single,pins = <
195			J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
196		>;
197	};
198
199	main_i2c0_pins_default: main-i2c0-pins-default {
200		pinctrl-single,pins = <
201			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
202			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
203		>;
204	};
205
206	main_i2c1_pins_default: main-i2c1-pins-default {
207		pinctrl-single,pins = <
208			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
209			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
210		>;
211	};
212
213	main_i2c3_pins_default: main-i2c3-pins-default {
214		pinctrl-single,pins = <
215			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
216			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
217		>;
218	};
219
220	main_i2c6_pins_default: main-i2c6-pins-default {
221		pinctrl-single,pins = <
222			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
223			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
224		>;
225	};
226
227	mcasp10_pins_default: mcasp10-pins-default {
228		pinctrl-single,pins = <
229			J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
230			J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
231			J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
232			J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
233			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
234			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
235			J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
236			J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
237			J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
238		>;
239	};
240
241	audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
242		pinctrl-single,pins = <
243			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
244		>;
245	};
246
247	main_mcan0_pins_default: main-mcan0-pins-default {
248		pinctrl-single,pins = <
249			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
250			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
251		>;
252	};
253
254	main_mcan2_pins_default: main-mcan2-pins-default {
255		pinctrl-single,pins = <
256			J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
257			J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
258		>;
259	};
260
261	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
262		pinctrl-single,pins = <
263			J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
264		>;
265	};
266};
267
268&wkup_pmx0 {
269	sw11_button_pins_default: sw11-button-pins-default {
270		pinctrl-single,pins = <
271			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
272		>;
273	};
274
275	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
276		pinctrl-single,pins = <
277			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
278			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
279			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
280			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
281			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
282			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
283			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
284			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
285		>;
286	};
287
288	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
289		pinctrl-single,pins = <
290			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
291			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
292			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
293			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
294			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
295			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
296			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
297			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
298			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
299			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
300			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
301			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
302		>;
303	};
304
305	mcu_mdio_pins_default: mcu-mdio1-pins-default {
306		pinctrl-single,pins = <
307			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
308			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
309		>;
310	};
311
312	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
313		pinctrl-single,pins = <
314			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
315			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
316		>;
317	};
318
319	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
320		pinctrl-single,pins = <
321			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
322			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
323		>;
324	};
325
326	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
327		pinctrl-single,pins = <
328			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
329			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
330		>;
331	};
332
333	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
334		pinctrl-single,pins = <
335			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
336		>;
337	};
338};
339
340&wkup_uart0 {
341	/* Wakeup UART is used by System firmware */
342	status = "reserved";
343};
344
345&main_uart0 {
346	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
347};
348
349&main_uart3 {
350	/* UART not brought out */
351	status = "disabled";
352};
353
354&main_uart5 {
355	/* UART not brought out */
356	status = "disabled";
357};
358
359&main_uart6 {
360	/* UART not brought out */
361	status = "disabled";
362};
363
364&main_uart7 {
365	/* UART not brought out */
366	status = "disabled";
367};
368
369&main_uart8 {
370	/* UART not brought out */
371	status = "disabled";
372};
373
374&main_uart9 {
375	/* UART not brought out */
376	status = "disabled";
377};
378
379&main_gpio2 {
380	status = "disabled";
381};
382
383&main_gpio3 {
384	status = "disabled";
385};
386
387&main_gpio4 {
388	status = "disabled";
389};
390
391&main_gpio5 {
392	status = "disabled";
393};
394
395&main_gpio6 {
396	status = "disabled";
397};
398
399&main_gpio7 {
400	status = "disabled";
401};
402
403&wkup_gpio1 {
404	status = "disabled";
405};
406
407&main_sdhci0 {
408	/* eMMC */
409	non-removable;
410	ti,driver-strength-ohm = <50>;
411	disable-wp;
412};
413
414&main_sdhci1 {
415	/* SD/MMC */
416	vmmc-supply = <&vdd_mmc1>;
417	vqmmc-supply = <&vdd_sd_dv_alt>;
418	pinctrl-names = "default";
419	pinctrl-0 = <&main_mmc1_pins_default>;
420	ti,driver-strength-ohm = <50>;
421	disable-wp;
422};
423
424&main_sdhci2 {
425	/* Unused */
426	status = "disabled";
427};
428
429&usb_serdes_mux {
430	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
431};
432
433&serdes_ln_ctrl {
434	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
435		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
436		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
437		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
438		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
439		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
440};
441
442&serdes_wiz3 {
443	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
444	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
445};
446
447&serdes3 {
448	serdes3_usb_link: phy@0 {
449		reg = <0>;
450		cdns,num-lanes = <2>;
451		#phy-cells = <0>;
452		cdns,phy-type = <PHY_TYPE_USB3>;
453		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
454	};
455};
456
457&usbss0 {
458	pinctrl-names = "default";
459	pinctrl-0 = <&main_usbss0_pins_default>;
460	ti,vbus-divider;
461};
462
463&usb0 {
464	dr_mode = "otg";
465	maximum-speed = "super-speed";
466	phys = <&serdes3_usb_link>;
467	phy-names = "cdns3,usb3-phy";
468};
469
470&usbss1 {
471	pinctrl-names = "default";
472	pinctrl-0 = <&main_usbss1_pins_default>;
473	ti,usb2-only;
474};
475
476&usb1 {
477	dr_mode = "host";
478	maximum-speed = "high-speed";
479};
480
481&ospi1 {
482	pinctrl-names = "default";
483	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
484
485	flash@0 {
486		compatible = "jedec,spi-nor";
487		reg = <0x0>;
488		spi-tx-bus-width = <1>;
489		spi-rx-bus-width = <4>;
490		spi-max-frequency = <40000000>;
491		cdns,tshsl-ns = <60>;
492		cdns,tsd2d-ns = <60>;
493		cdns,tchsh-ns = <60>;
494		cdns,tslch-ns = <60>;
495		cdns,read-delay = <2>;
496	};
497};
498
499&tscadc0 {
500	adc {
501		ti,adc-channels = <0 1 2 3 4 5 6 7>;
502	};
503};
504
505&tscadc1 {
506	adc {
507		ti,adc-channels = <0 1 2 3 4 5 6 7>;
508	};
509};
510
511&main_i2c0 {
512	pinctrl-names = "default";
513	pinctrl-0 = <&main_i2c0_pins_default>;
514	clock-frequency = <400000>;
515
516	exp1: gpio@20 {
517		compatible = "ti,tca6416";
518		reg = <0x20>;
519		gpio-controller;
520		#gpio-cells = <2>;
521	};
522
523	exp2: gpio@22 {
524		compatible = "ti,tca6424";
525		reg = <0x22>;
526		gpio-controller;
527		#gpio-cells = <2>;
528
529		p09-hog {
530			/* P11 - MCASP/TRACE_MUX_S0 */
531			gpio-hog;
532			gpios = <9 GPIO_ACTIVE_HIGH>;
533			output-low;
534			line-name = "MCASP/TRACE_MUX_S0";
535		};
536
537		p10-hog {
538			/* P12 - MCASP/TRACE_MUX_S1 */
539			gpio-hog;
540			gpios = <10 GPIO_ACTIVE_HIGH>;
541			output-high;
542			line-name = "MCASP/TRACE_MUX_S1";
543		};
544	};
545};
546
547&main_i2c1 {
548	pinctrl-names = "default";
549	pinctrl-0 = <&main_i2c1_pins_default>;
550	clock-frequency = <400000>;
551
552	exp4: gpio@20 {
553		compatible = "ti,tca6408";
554		reg = <0x20>;
555		gpio-controller;
556		#gpio-cells = <2>;
557		pinctrl-names = "default";
558		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
559		interrupt-parent = <&main_gpio1>;
560		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
561		interrupt-controller;
562		#interrupt-cells = <2>;
563	};
564};
565
566&k3_clks {
567	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
568	pinctrl-names = "default";
569	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
570};
571
572&main_i2c3 {
573	pinctrl-names = "default";
574	pinctrl-0 = <&main_i2c3_pins_default>;
575	clock-frequency = <400000>;
576
577	exp3: gpio@20 {
578		compatible = "ti,tca6408";
579		reg = <0x20>;
580		gpio-controller;
581		#gpio-cells = <2>;
582	};
583
584	pcm3168a_1: audio-codec@44 {
585		compatible = "ti,pcm3168a";
586		reg = <0x44>;
587
588		#sound-dai-cells = <1>;
589
590		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
591
592		/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
593		clocks = <&k3_clks 157 371>;
594		clock-names = "scki";
595
596		/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
597		assigned-clocks = <&k3_clks 157 371>;
598		assigned-clock-parents = <&k3_clks 157 400>;
599		assigned-clock-rates = <24576000>; /* for 48KHz */
600
601		VDD1-supply = <&vsys_3v3>;
602		VDD2-supply = <&vsys_3v3>;
603		VCCAD1-supply = <&vsys_5v0>;
604		VCCAD2-supply = <&vsys_5v0>;
605		VCCDA1-supply = <&vsys_5v0>;
606		VCCDA2-supply = <&vsys_5v0>;
607	};
608};
609
610&main_i2c6 {
611	pinctrl-names = "default";
612	pinctrl-0 = <&main_i2c6_pins_default>;
613	clock-frequency = <400000>;
614
615	exp5: gpio@20 {
616		compatible = "ti,tca6408";
617		reg = <0x20>;
618		gpio-controller;
619		#gpio-cells = <2>;
620	};
621};
622
623&mcu_cpsw {
624	pinctrl-names = "default";
625	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
626};
627
628&davinci_mdio {
629	phy0: ethernet-phy@0 {
630		reg = <0>;
631		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
632		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
633	};
634};
635
636&cpsw_port1 {
637	phy-mode = "rgmii-rxid";
638	phy-handle = <&phy0>;
639};
640
641&dss {
642	/*
643	 * These clock assignments are chosen to enable the following outputs:
644	 *
645	 * VP0 - DisplayPort SST
646	 * VP1 - DPI0
647	 * VP2 - DSI
648	 * VP3 - DPI1
649	 */
650
651	assigned-clocks = <&k3_clks 152 1>,
652			  <&k3_clks 152 4>,
653			  <&k3_clks 152 9>,
654			  <&k3_clks 152 13>;
655	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
656				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
657				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
658				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
659};
660
661&mcasp0 {
662	status = "disabled";
663};
664
665&mcasp1 {
666	status = "disabled";
667};
668
669&mcasp2 {
670	status = "disabled";
671};
672
673&mcasp3 {
674	status = "disabled";
675};
676
677&mcasp4 {
678	status = "disabled";
679};
680
681&mcasp5 {
682	status = "disabled";
683};
684
685&mcasp6 {
686	status = "disabled";
687};
688
689&mcasp7 {
690	status = "disabled";
691};
692
693&mcasp8 {
694	status = "disabled";
695};
696
697&mcasp9 {
698	status = "disabled";
699};
700
701&mcasp10 {
702	#sound-dai-cells = <0>;
703
704	pinctrl-names = "default";
705	pinctrl-0 = <&mcasp10_pins_default>;
706
707	op-mode = <0>;          /* MCASP_IIS_MODE */
708	tdm-slots = <2>;
709	auxclk-fs-ratio = <256>;
710
711	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
712		1 1 1 1
713		2 2 2 0
714	>;
715	tx-num-evt = <0>;
716	rx-num-evt = <0>;
717};
718
719&mcasp11 {
720	status = "disabled";
721};
722
723&cmn_refclk1 {
724	clock-frequency = <100000000>;
725};
726
727&wiz0_pll1_refclk {
728	assigned-clocks = <&wiz0_pll1_refclk>;
729	assigned-clock-parents = <&cmn_refclk1>;
730};
731
732&wiz0_refclk_dig {
733	assigned-clocks = <&wiz0_refclk_dig>;
734	assigned-clock-parents = <&cmn_refclk1>;
735};
736
737&wiz1_pll1_refclk {
738	assigned-clocks = <&wiz1_pll1_refclk>;
739	assigned-clock-parents = <&cmn_refclk1>;
740};
741
742&wiz1_refclk_dig {
743	assigned-clocks = <&wiz1_refclk_dig>;
744	assigned-clock-parents = <&cmn_refclk1>;
745};
746
747&wiz2_pll1_refclk {
748	assigned-clocks = <&wiz2_pll1_refclk>;
749	assigned-clock-parents = <&cmn_refclk1>;
750};
751
752&wiz2_refclk_dig {
753	assigned-clocks = <&wiz2_refclk_dig>;
754	assigned-clock-parents = <&cmn_refclk1>;
755};
756
757&serdes0 {
758	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
759	assigned-clock-parents = <&wiz0_pll1_refclk>;
760
761	serdes0_pcie_link: phy@0 {
762		reg = <0>;
763		cdns,num-lanes = <1>;
764		#phy-cells = <0>;
765		cdns,phy-type = <PHY_TYPE_PCIE>;
766		resets = <&serdes_wiz0 1>;
767	};
768};
769
770&serdes1 {
771	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
772	assigned-clock-parents = <&wiz1_pll1_refclk>;
773
774	serdes1_pcie_link: phy@0 {
775		reg = <0>;
776		cdns,num-lanes = <2>;
777		#phy-cells = <0>;
778		cdns,phy-type = <PHY_TYPE_PCIE>;
779		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
780	};
781};
782
783&serdes2 {
784	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
785	assigned-clock-parents = <&wiz2_pll1_refclk>;
786
787	serdes2_pcie_link: phy@0 {
788		reg = <0>;
789		cdns,num-lanes = <2>;
790		#phy-cells = <0>;
791		cdns,phy-type = <PHY_TYPE_PCIE>;
792		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
793	};
794};
795
796&pcie0_rc {
797	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
798	phys = <&serdes0_pcie_link>;
799	phy-names = "pcie-phy";
800	num-lanes = <1>;
801};
802
803&pcie1_rc {
804	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
805	phys = <&serdes1_pcie_link>;
806	phy-names = "pcie-phy";
807	num-lanes = <2>;
808};
809
810&pcie2_rc {
811	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
812	phys = <&serdes2_pcie_link>;
813	phy-names = "pcie-phy";
814	num-lanes = <2>;
815};
816
817&pcie0_ep {
818	phys = <&serdes0_pcie_link>;
819	phy-names = "pcie-phy";
820	num-lanes = <1>;
821	status = "disabled";
822};
823
824&pcie1_ep {
825	phys = <&serdes1_pcie_link>;
826	phy-names = "pcie-phy";
827	num-lanes = <2>;
828	status = "disabled";
829};
830
831&pcie2_ep {
832	phys = <&serdes2_pcie_link>;
833	phy-names = "pcie-phy";
834	num-lanes = <2>;
835	status = "disabled";
836};
837
838&pcie3_rc {
839	status = "disabled";
840};
841
842&pcie3_ep {
843	status = "disabled";
844};
845
846&dss {
847	status = "disabled";
848};
849
850&icssg0_mdio {
851	status = "disabled";
852};
853
854&icssg1_mdio {
855	status = "disabled";
856};
857
858&mcu_mcan0 {
859	pinctrl-names = "default";
860	pinctrl-0 = <&mcu_mcan0_pins_default>;
861	phys = <&transceiver1>;
862};
863
864&mcu_mcan1 {
865	pinctrl-names = "default";
866	pinctrl-0 = <&mcu_mcan1_pins_default>;
867	phys = <&transceiver2>;
868};
869
870&main_mcan0 {
871	pinctrl-names = "default";
872	pinctrl-0 = <&main_mcan0_pins_default>;
873	phys = <&transceiver3>;
874};
875
876&main_mcan1 {
877	status = "disabled";
878};
879
880&main_mcan2 {
881	pinctrl-names = "default";
882	pinctrl-0 = <&main_mcan2_pins_default>;
883	phys = <&transceiver4>;
884};
885
886&main_mcan3 {
887	status = "disabled";
888};
889
890&main_mcan4 {
891	status = "disabled";
892};
893
894&main_mcan5 {
895	status = "disabled";
896};
897
898&main_mcan6 {
899	status = "disabled";
900};
901
902&main_mcan7 {
903	status = "disabled";
904};
905
906&main_mcan8 {
907	status = "disabled";
908};
909
910&main_mcan9 {
911	status = "disabled";
912};
913
914&main_mcan10 {
915	status = "disabled";
916};
917
918&main_mcan11 {
919	status = "disabled";
920};
921
922&main_mcan12 {
923	status = "disabled";
924};
925
926&main_mcan13 {
927	status = "disabled";
928};
929