1// SPDX-License-Identifier: GPL-2.0 2/* 3 * https://beagleboard.org/ai-64 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation 6 * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation 7 */ 8 9/dts-v1/; 10 11#include "k3-j721e.dtsi" 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/leds/common.h> 15#include <dt-bindings/net/ti-dp83867.h> 16#include <dt-bindings/phy/phy-cadence.h> 17 18/ { 19 compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; 20 model = "BeagleBoard.org BeagleBone AI-64"; 21 22 aliases { 23 serial2 = &main_uart0; 24 mmc0 = &main_sdhci0; 25 mmc1 = &main_sdhci1; 26 i2c0 = &wkup_i2c0; 27 i2c1 = &main_i2c6; 28 i2c2 = &main_i2c2; 29 i2c3 = &main_i2c4; 30 }; 31 32 chosen { 33 stdout-path = "serial2:115200n8"; 34 }; 35 36 memory@80000000 { 37 device_type = "memory"; 38 /* 4G RAM */ 39 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 40 <0x00000008 0x80000000 0x00000000 0x80000000>; 41 }; 42 43 reserved_memory: reserved-memory { 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 48 secure_ddr: optee@9e800000 { 49 reg = <0x00 0x9e800000 0x00 0x01800000>; 50 no-map; 51 }; 52 53 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa0000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa0100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa1000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa1100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa2000000 0x00 0x100000>; 80 no-map; 81 }; 82 83 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa2100000 0x00 0xf00000>; 86 no-map; 87 }; 88 89 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa3000000 0x00 0x100000>; 92 no-map; 93 }; 94 95 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa3100000 0x00 0xf00000>; 98 no-map; 99 }; 100 101 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa4000000 0x00 0x100000>; 104 no-map; 105 }; 106 107 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 108 compatible = "shared-dma-pool"; 109 reg = <0x00 0xa4100000 0x00 0xf00000>; 110 no-map; 111 }; 112 113 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 114 compatible = "shared-dma-pool"; 115 reg = <0x00 0xa5000000 0x00 0x100000>; 116 no-map; 117 }; 118 119 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 120 compatible = "shared-dma-pool"; 121 reg = <0x00 0xa5100000 0x00 0xf00000>; 122 no-map; 123 }; 124 125 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 126 compatible = "shared-dma-pool"; 127 reg = <0x00 0xa6000000 0x00 0x100000>; 128 no-map; 129 }; 130 131 c66_0_memory_region: c66-memory@a6100000 { 132 compatible = "shared-dma-pool"; 133 reg = <0x00 0xa6100000 0x00 0xf00000>; 134 no-map; 135 }; 136 137 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 138 compatible = "shared-dma-pool"; 139 reg = <0x00 0xa7000000 0x00 0x100000>; 140 no-map; 141 }; 142 143 c66_1_memory_region: c66-memory@a7100000 { 144 compatible = "shared-dma-pool"; 145 reg = <0x00 0xa7100000 0x00 0xf00000>; 146 no-map; 147 }; 148 149 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 150 compatible = "shared-dma-pool"; 151 reg = <0x00 0xa8000000 0x00 0x100000>; 152 no-map; 153 }; 154 155 c71_0_memory_region: c71-memory@a8100000 { 156 compatible = "shared-dma-pool"; 157 reg = <0x00 0xa8100000 0x00 0xf00000>; 158 no-map; 159 }; 160 161 rtos_ipc_memory_region: ipc-memories@aa000000 { 162 reg = <0x00 0xaa000000 0x00 0x01c00000>; 163 alignment = <0x1000>; 164 no-map; 165 }; 166 }; 167 168 gpio_keys: gpio-keys { 169 compatible = "gpio-keys"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&sw_pwr_pins_default>; 172 173 button-1 { 174 label = "BOOT"; 175 linux,code = <BTN_0>; 176 gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; 177 }; 178 179 button-2 { 180 label = "POWER"; 181 linux,code = <KEY_POWER>; 182 gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; 183 }; 184 }; 185 186 leds { 187 compatible = "gpio-leds"; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&led_pins_default>; 190 191 led-0 { 192 gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; 193 function = LED_FUNCTION_HEARTBEAT; 194 linux,default-trigger = "heartbeat"; 195 }; 196 197 led-1 { 198 gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; 199 function = LED_FUNCTION_DISK_ACTIVITY; 200 linux,default-trigger = "mmc0"; 201 }; 202 203 led-2 { 204 gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; 205 function = LED_FUNCTION_CPU; 206 linux,default-trigger = "cpu"; 207 }; 208 209 led-3 { 210 gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; 211 function = LED_FUNCTION_DISK_ACTIVITY; 212 linux,default-trigger = "mmc1"; 213 }; 214 215 led-4 { 216 gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; 217 function = LED_FUNCTION_WLAN; 218 default-state = "off"; 219 }; 220 }; 221 222 evm_12v0: regulator-0 { 223 /* main supply */ 224 compatible = "regulator-fixed"; 225 regulator-name = "evm_12v0"; 226 regulator-min-microvolt = <12000000>; 227 regulator-max-microvolt = <12000000>; 228 regulator-always-on; 229 regulator-boot-on; 230 }; 231 232 vsys_3v3: regulator-1 { 233 /* Output of LMS140 */ 234 compatible = "regulator-fixed"; 235 regulator-name = "vsys_3v3"; 236 regulator-min-microvolt = <3300000>; 237 regulator-max-microvolt = <3300000>; 238 vin-supply = <&evm_12v0>; 239 regulator-always-on; 240 regulator-boot-on; 241 }; 242 243 vsys_5v0: regulator-2 { 244 /* Output of LM5140 */ 245 compatible = "regulator-fixed"; 246 regulator-name = "vsys_5v0"; 247 regulator-min-microvolt = <5000000>; 248 regulator-max-microvolt = <5000000>; 249 vin-supply = <&evm_12v0>; 250 regulator-always-on; 251 regulator-boot-on; 252 }; 253 254 vdd_mmc1: regulator-3 { 255 compatible = "regulator-fixed"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&sd_pwr_en_pins_default>; 258 regulator-name = "vdd_mmc1"; 259 regulator-min-microvolt = <3300000>; 260 regulator-max-microvolt = <3300000>; 261 regulator-boot-on; 262 enable-active-high; 263 vin-supply = <&vsys_3v3>; 264 gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; 265 }; 266 267 vdd_sd_dv_alt: regulator-4 { 268 compatible = "regulator-gpio"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 271 regulator-name = "tlv71033"; 272 regulator-min-microvolt = <1800000>; 273 regulator-max-microvolt = <3300000>; 274 regulator-boot-on; 275 vin-supply = <&vsys_5v0>; 276 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 277 states = <1800000 0x0>, 278 <3300000 0x1>; 279 }; 280 281 dp_pwr_3v3: regulator-5 { 282 compatible = "regulator-fixed"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&dp0_3v3_en_pins_default>; 285 regulator-name = "dp-pwr"; 286 regulator-min-microvolt = <3300000>; 287 regulator-max-microvolt = <3300000>; 288 gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ 289 enable-active-high; 290 }; 291 292 dp0: connector { 293 compatible = "dp-connector"; 294 label = "DP0"; 295 type = "full-size"; 296 dp-pwr-supply = <&dp_pwr_3v3>; 297 298 port { 299 dp_connector_in: endpoint { 300 remote-endpoint = <&dp0_out>; 301 }; 302 }; 303 }; 304}; 305 306&main_pmx0 { 307 led_pins_default: led-pins-default { 308 pinctrl-single,pins = < 309 J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ 310 J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ 311 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 312 J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ 313 J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ 314 >; 315 }; 316 317 main_mmc1_pins_default: main-mmc1-pins-default { 318 pinctrl-single,pins = < 319 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 320 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 321 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 322 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 323 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 324 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 325 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 326 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 327 >; 328 }; 329 330 main_uart0_pins_default: main-uart0-pins-default { 331 pinctrl-single,pins = < 332 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 333 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 334 >; 335 }; 336 337 sd_pwr_en_pins_default: sd-pwr-en-pins-default { 338 pinctrl-single,pins = < 339 J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 340 >; 341 }; 342 343 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 344 pinctrl-single,pins = < 345 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 346 >; 347 }; 348 349 main_usbss0_pins_default: main-usbss0-pins-default { 350 pinctrl-single,pins = < 351 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ 352 >; 353 }; 354 355 main_usbss1_pins_default: main-usbss1-pins-default { 356 pinctrl-single,pins = < 357 J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ 358 >; 359 }; 360 361 dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { 362 pinctrl-single,pins = < 363 J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ 364 >; 365 }; 366 367 dp0_pins_default: dp0-pins-default { 368 pinctrl-single,pins = < 369 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ 370 >; 371 }; 372 373 main_i2c0_pins_default: main-i2c0-pins-default { 374 pinctrl-single,pins = < 375 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 376 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 377 >; 378 }; 379 380 main_i2c1_pins_default: main-i2c1-pins-default { 381 pinctrl-single,pins = < 382 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 383 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 384 >; 385 }; 386 387 main_i2c2_pins_default: main-i2c2-pins-default { 388 pinctrl-single,pins = < 389 J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ 390 J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ 391 J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ 392 J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ 393 >; 394 }; 395 396 main_i2c3_pins_default: main-i2c3-pins-default { 397 pinctrl-single,pins = < 398 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 399 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 400 >; 401 }; 402 403 main_i2c4_pins_default: main-i2c4-pins-default { 404 pinctrl-single,pins = < 405 J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ 406 J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ 407 J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ 408 J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ 409 >; 410 }; 411 412 main_i2c5_pins_default: main-i2c5-pins-default { 413 pinctrl-single,pins = < 414 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 415 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 416 >; 417 }; 418 419 main_i2c6_pins_default: main-i2c6-pins-default { 420 pinctrl-single,pins = < 421 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 422 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 423 J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ 424 J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ 425 >; 426 }; 427 428 csi0_gpio_pins_default: csi0-gpio-pins-default { 429 pinctrl-single,pins = < 430 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 431 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 432 >; 433 }; 434 435 csi1_gpio_pins_default: csi1-gpio-pins-default { 436 pinctrl-single,pins = < 437 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 438 J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 439 >; 440 }; 441 442 pcie1_rst_pins_default: pcie1-rst-pins-default { 443 pinctrl-single,pins = < 444 J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ 445 >; 446 }; 447}; 448 449&wkup_pmx0 { 450 eeprom_wp_pins_default: eeprom-wp-pins-default { 451 pinctrl-single,pins = < 452 J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ 453 >; 454 }; 455 456 mcu_adc0_pins_default: mcu-adc0-pins-default { 457 pinctrl-single,pins = < 458 J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ 459 J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ 460 J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ 461 J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ 462 J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ 463 J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ 464 J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ 465 >; 466 }; 467 468 mcu_adc1_pins_default: mcu-adc1-pins-default { 469 pinctrl-single,pins = < 470 J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ 471 >; 472 }; 473 474 mikro_bus_pins_default: mikro-bus-pins-default { 475 pinctrl-single,pins = < 476 J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ 477 J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 478 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ 479 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ 480 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ 481 482 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ 483 J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ 484 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ 485 J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ 486 487 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ 488 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ 489 490 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ 491 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ 492 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ 493 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ 494 >; 495 }; 496 497 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 498 pinctrl-single,pins = < 499 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 500 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 501 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 502 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 503 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 504 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 505 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 506 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 507 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 508 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 509 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 510 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 511 >; 512 }; 513 514 mcu_mdio_pins_default: mcu-mdio1-pins-default { 515 pinctrl-single,pins = < 516 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 517 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 518 >; 519 }; 520 521 sw_pwr_pins_default: sw-pwr-pins-default { 522 pinctrl-single,pins = < 523 J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ 524 >; 525 }; 526 527 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 528 pinctrl-single,pins = < 529 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 530 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 531 >; 532 }; 533 534 mcu_usbss1_pins_default: mcu-usbss1-pins-default { 535 pinctrl-single,pins = < 536 J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ 537 >; 538 }; 539}; 540 541&wkup_uart0 { 542 /* Wakeup UART is used by TIFS firmware. */ 543 status = "reserved"; 544}; 545 546&main_uart0 { 547 status = "okay"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&main_uart0_pins_default>; 550 /* Shared with ATF on this platform */ 551 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 552}; 553 554&main_sdhci0 { 555 /* eMMC */ 556 non-removable; 557 ti,driver-strength-ohm = <50>; 558 disable-wp; 559}; 560 561&main_sdhci1 { 562 /* SD Card */ 563 vmmc-supply = <&vdd_mmc1>; 564 vqmmc-supply = <&vdd_sd_dv_alt>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&main_mmc1_pins_default>; 567 ti,driver-strength-ohm = <50>; 568 disable-wp; 569}; 570 571&main_sdhci2 { 572 /* Unused */ 573 status = "disabled"; 574}; 575 576&ospi0 { 577 /* Unused */ 578 status = "disabled"; 579}; 580 581&ospi1 { 582 /* Unused */ 583 status = "disabled"; 584}; 585 586&main_i2c0 { 587 status = "okay"; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&main_i2c0_pins_default>; 590 clock-frequency = <400000>; 591}; 592 593&main_i2c1 { 594 status = "okay"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; 597 clock-frequency = <400000>; 598}; 599 600&main_i2c2 { 601 /* BBB Header: P9.19 and P9.20 */ 602 status = "okay"; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&main_i2c2_pins_default>; 605 clock-frequency = <100000>; 606}; 607 608&main_i2c3 { 609 status = "okay"; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&main_i2c3_pins_default>; 612 clock-frequency = <400000>; 613}; 614 615&main_i2c4 { 616 /* BBB Header: P9.24 and P9.26 */ 617 status = "okay"; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&main_i2c4_pins_default>; 620 clock-frequency = <100000>; 621}; 622 623&main_i2c5 { 624 status = "okay"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; 627 clock-frequency = <400000>; 628}; 629 630&main_i2c6 { 631 /* BBB Header: P9.17 and P9.18 */ 632 status = "okay"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&main_i2c6_pins_default>; 635 clock-frequency = <100000>; 636 status = "okay"; 637}; 638 639&wkup_i2c0 { 640 status = "okay"; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; 643 clock-frequency = <400000>; 644 645 eeprom@50 { 646 compatible = "atmel,24c04"; 647 reg = <0x50>; 648 }; 649}; 650 651&main_gpio2 { 652 /* Unused */ 653 status = "disabled"; 654}; 655 656&main_gpio3 { 657 /* Unused */ 658 status = "disabled"; 659}; 660 661&main_gpio4 { 662 /* Unused */ 663 status = "disabled"; 664}; 665 666&main_gpio5 { 667 /* Unused */ 668 status = "disabled"; 669}; 670 671&main_gpio6 { 672 /* Unused */ 673 status = "disabled"; 674}; 675 676&main_gpio7 { 677 /* Unused */ 678 status = "disabled"; 679}; 680 681&wkup_gpio0 { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; 684}; 685 686&wkup_gpio1 { 687 /* Unused */ 688 status = "disabled"; 689}; 690 691&usb_serdes_mux { 692 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 693}; 694 695&serdes_ln_ctrl { 696 idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 697 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 698 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 699 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 700 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 701 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 702}; 703 704&serdes_wiz3 { 705 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; 706 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 707}; 708 709&serdes3 { 710 serdes3_usb_link: phy@0 { 711 reg = <0>; 712 cdns,num-lanes = <2>; 713 #phy-cells = <0>; 714 cdns,phy-type = <PHY_TYPE_USB3>; 715 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 716 }; 717}; 718 719&serdes4 { 720 torrent_phy_dp: phy@0 { 721 reg = <0>; 722 resets = <&serdes_wiz4 1>; 723 cdns,phy-type = <PHY_TYPE_DP>; 724 cdns,num-lanes = <4>; 725 cdns,max-bit-rate = <5400>; 726 #phy-cells = <0>; 727 }; 728}; 729 730&mhdp { 731 phys = <&torrent_phy_dp>; 732 phy-names = "dpphy"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&dp0_pins_default>; 735}; 736 737&usbss0 { 738 pinctrl-names = "default"; 739 pinctrl-0 = <&main_usbss0_pins_default>; 740 ti,vbus-divider; 741}; 742 743&usb0 { 744 dr_mode = "peripheral"; 745 maximum-speed = "super-speed"; 746 phys = <&serdes3_usb_link>; 747 phy-names = "cdns3,usb3-phy"; 748}; 749 750&serdes2 { 751 serdes2_usb_link: phy@1 { 752 reg = <1>; 753 cdns,num-lanes = <1>; 754 #phy-cells = <0>; 755 cdns,phy-type = <PHY_TYPE_USB3>; 756 resets = <&serdes_wiz2 2>; 757 }; 758}; 759 760&usbss1 { 761 pinctrl-names = "default"; 762 pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; 763 ti,vbus-divider; 764}; 765 766&usb1 { 767 dr_mode = "host"; 768 maximum-speed = "super-speed"; 769 phys = <&serdes2_usb_link>; 770 phy-names = "cdns3,usb3-phy"; 771}; 772 773&tscadc0 { 774 /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ 775 adc { 776 ti,adc-channels = <0 1 2 3 4 5 6>; 777 }; 778}; 779 780&tscadc1 { 781 /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ 782 adc { 783 ti,adc-channels = <0>; 784 }; 785}; 786 787&mcu_cpsw { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&mcu_cpsw_pins_default>; 790}; 791 792&davinci_mdio { 793 pinctrl-names = "default"; 794 pinctrl-0 = <&mcu_mdio_pins_default>; 795 796 phy0: ethernet-phy@0 { 797 reg = <0>; 798 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 799 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 800 }; 801}; 802 803&cpsw_port1 { 804 phy-mode = "rgmii-rxid"; 805 phy-handle = <&phy0>; 806}; 807 808&dss { 809 /* 810 * These clock assignments are chosen to enable the following outputs: 811 * 812 * VP0 - DisplayPort SST 813 * VP1 - DPI0 814 * VP2 - DSI 815 * VP3 - DPI1 816 */ 817 818 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 819 <&k3_clks 152 4>, /* VP 2 pixel clock */ 820 <&k3_clks 152 9>, /* VP 3 pixel clock */ 821 <&k3_clks 152 13>; /* VP 4 pixel clock */ 822 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 823 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 824 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 825 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 826}; 827 828&dss_ports { 829 port { 830 dpi0_out: endpoint { 831 remote-endpoint = <&dp0_in>; 832 }; 833 }; 834}; 835 836&dp0_ports { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 840 port@0 { 841 reg = <0>; 842 dp0_in: endpoint { 843 remote-endpoint = <&dpi0_out>; 844 }; 845 }; 846 847 port@4 { 848 reg = <4>; 849 dp0_out: endpoint { 850 remote-endpoint = <&dp_connector_in>; 851 }; 852 }; 853}; 854 855&serdes0 { 856 serdes0_pcie_link: phy@0 { 857 reg = <0>; 858 cdns,num-lanes = <1>; 859 #phy-cells = <0>; 860 cdns,phy-type = <PHY_TYPE_PCIE>; 861 resets = <&serdes_wiz0 1>; 862 }; 863}; 864 865&serdes1 { 866 serdes1_pcie_link: phy@0 { 867 reg = <0>; 868 cdns,num-lanes = <2>; 869 #phy-cells = <0>; 870 cdns,phy-type = <PHY_TYPE_PCIE>; 871 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 872 }; 873}; 874 875&pcie0_rc { 876 /* Unused */ 877 status = "disabled"; 878}; 879 880&pcie1_rc { 881 pinctrl-names = "default"; 882 pinctrl-0 = <&pcie1_rst_pins_default>; 883 phys = <&serdes1_pcie_link>; 884 phy-names = "pcie-phy"; 885 num-lanes = <2>; 886 max-link-speed = <3>; 887 reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; 888}; 889 890&pcie2_rc { 891 /* Unused */ 892 status = "disabled"; 893}; 894 895&pcie0_ep { 896 status = "disabled"; 897 phys = <&serdes0_pcie_link>; 898 phy-names = "pcie-phy"; 899 num-lanes = <1>; 900}; 901 902&pcie1_ep { 903 status = "disabled"; 904 phys = <&serdes1_pcie_link>; 905 phy-names = "pcie-phy"; 906 num-lanes = <2>; 907}; 908 909&pcie2_ep { 910 /* Unused */ 911 status = "disabled"; 912}; 913 914&pcie3_rc { 915 /* Unused */ 916 status = "disabled"; 917}; 918 919&pcie3_ep { 920 /* Unused */ 921 status = "disabled"; 922}; 923 924&icssg0_mdio { 925 /* Unused */ 926 status = "disabled"; 927}; 928 929&icssg1_mdio { 930 /* Unused */ 931 status = "disabled"; 932}; 933 934&ufs_wrapper { 935 status = "disabled"; 936}; 937 938&mailbox0_cluster0 { 939 interrupts = <436>; 940 941 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 942 ti,mbox-rx = <0 0 0>; 943 ti,mbox-tx = <1 0 0>; 944 }; 945 946 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 947 ti,mbox-rx = <2 0 0>; 948 ti,mbox-tx = <3 0 0>; 949 }; 950}; 951 952&mailbox0_cluster1 { 953 interrupts = <432>; 954 955 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 956 ti,mbox-rx = <0 0 0>; 957 ti,mbox-tx = <1 0 0>; 958 }; 959 960 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 961 ti,mbox-rx = <2 0 0>; 962 ti,mbox-tx = <3 0 0>; 963 }; 964}; 965 966&mailbox0_cluster2 { 967 interrupts = <428>; 968 969 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 970 ti,mbox-rx = <0 0 0>; 971 ti,mbox-tx = <1 0 0>; 972 }; 973 974 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 975 ti,mbox-rx = <2 0 0>; 976 ti,mbox-tx = <3 0 0>; 977 }; 978}; 979 980&mailbox0_cluster3 { 981 interrupts = <424>; 982 983 mbox_c66_0: mbox-c66-0 { 984 ti,mbox-rx = <0 0 0>; 985 ti,mbox-tx = <1 0 0>; 986 }; 987 988 mbox_c66_1: mbox-c66-1 { 989 ti,mbox-rx = <2 0 0>; 990 ti,mbox-tx = <3 0 0>; 991 }; 992}; 993 994&mailbox0_cluster4 { 995 interrupts = <420>; 996 997 mbox_c71_0: mbox-c71-0 { 998 ti,mbox-rx = <0 0 0>; 999 ti,mbox-tx = <1 0 0>; 1000 }; 1001}; 1002 1003&mcu_r5fss0_core0 { 1004 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1005 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1006 <&mcu_r5fss0_core0_memory_region>; 1007}; 1008 1009&mcu_r5fss0_core1 { 1010 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1011 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1012 <&mcu_r5fss0_core1_memory_region>; 1013}; 1014 1015&main_r5fss0_core0 { 1016 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1017 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1018 <&main_r5fss0_core0_memory_region>; 1019}; 1020 1021&main_r5fss0_core1 { 1022 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1023 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1024 <&main_r5fss0_core1_memory_region>; 1025}; 1026 1027&main_r5fss1_core0 { 1028 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1029 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1030 <&main_r5fss1_core0_memory_region>; 1031}; 1032 1033&main_r5fss1_core1 { 1034 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1035 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1036 <&main_r5fss1_core1_memory_region>; 1037}; 1038 1039&c66_0 { 1040 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1041 memory-region = <&c66_0_dma_memory_region>, 1042 <&c66_0_memory_region>; 1043}; 1044 1045&c66_1 { 1046 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1047 memory-region = <&c66_1_dma_memory_region>, 1048 <&c66_1_memory_region>; 1049}; 1050 1051&c71_0 { 1052 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1053 memory-region = <&c71_0_dma_memory_region>, 1054 <&c71_0_memory_region>; 1055}; 1056