1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200.dtsi" 9 10/ { 11 memory@80000000 { 12 device_type = "memory"; 13 /* 4G RAM */ 14 reg = <0x00 0x80000000 0x00 0x80000000>, 15 <0x08 0x80000000 0x00 0x80000000>; 16 }; 17 18 reserved_memory: reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 secure_ddr: optee@9e800000 { 24 reg = <0x00 0x9e800000 0x00 0x01800000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 30 compatible = "shared-dma-pool"; 31 reg = <0x00 0xa0000000 0x00 0x100000>; 32 no-map; 33 }; 34 35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 36 compatible = "shared-dma-pool"; 37 reg = <0x00 0xa0100000 0x00 0xf00000>; 38 no-map; 39 }; 40 41 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa1000000 0x00 0x100000>; 44 no-map; 45 }; 46 47 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa1100000 0x00 0xf00000>; 50 no-map; 51 }; 52 53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa2000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa2100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa3000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa3100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 rtos_ipc_memory_region: ipc-memories@a4000000 { 78 reg = <0x00 0xa4000000 0x00 0x00800000>; 79 alignment = <0x1000>; 80 no-map; 81 }; 82 }; 83}; 84 85&wkup_pmx0 { 86 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 87 pinctrl-single,pins = < 88 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 89 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 90 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 91 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 92 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 93 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 94 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 95 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 96 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 97 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 98 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 99 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 100 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 101 >; 102 }; 103 104 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 105 pinctrl-single,pins = < 106 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 107 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 108 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 109 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 110 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 111 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 112 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 113 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 114 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 115 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 116 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 117 >; 118 }; 119}; 120 121&wkup_pmx2 { 122 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 123 pinctrl-single,pins = < 124 J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ 125 J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ 126 >; 127 }; 128}; 129 130&wkup_pmx3 { 131 pmic_irq_pins_default: pmic-irq-default-pins { 132 pinctrl-single,pins = < 133 J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ 134 >; 135 }; 136}; 137 138&main_pmx0 { 139 main_i2c0_pins_default: main-i2c0-default-pins { 140 pinctrl-single,pins = < 141 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 142 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 143 >; 144 }; 145}; 146 147&hbmc { 148 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 149 * appropriate node based on board detection 150 */ 151 status = "disabled"; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 154 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 155 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 156 157 flash@0,0 { 158 compatible = "cypress,hyperflash", "cfi-flash"; 159 reg = <0x00 0x00 0x4000000>; 160 161 partitions { 162 compatible = "fixed-partitions"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 166 partition@0 { 167 label = "hbmc.tiboot3"; 168 reg = <0x0 0x100000>; 169 }; 170 171 partition@100000 { 172 label = "hbmc.tispl"; 173 reg = <0x100000 0x200000>; 174 }; 175 176 partition@300000 { 177 label = "hbmc.u-boot"; 178 reg = <0x300000 0x400000>; 179 }; 180 181 partition@700000 { 182 label = "hbmc.env"; 183 reg = <0x700000 0x40000>; 184 }; 185 186 partition@800000 { 187 label = "hbmc.rootfs"; 188 reg = <0x800000 0x3800000>; 189 }; 190 }; 191 }; 192}; 193 194&mailbox0_cluster0 { 195 status = "okay"; 196 interrupts = <436>; 197 198 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 199 ti,mbox-rx = <0 0 0>; 200 ti,mbox-tx = <1 0 0>; 201 }; 202 203 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 204 ti,mbox-rx = <2 0 0>; 205 ti,mbox-tx = <3 0 0>; 206 }; 207}; 208 209&mailbox0_cluster1 { 210 status = "okay"; 211 interrupts = <432>; 212 213 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 214 ti,mbox-rx = <0 0 0>; 215 ti,mbox-tx = <1 0 0>; 216 }; 217 218 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 219 ti,mbox-rx = <2 0 0>; 220 ti,mbox-tx = <3 0 0>; 221 }; 222}; 223 224&mcu_r5fss0_core0 { 225 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; 226 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 227 <&mcu_r5fss0_core0_memory_region>; 228}; 229 230&mcu_r5fss0_core1 { 231 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; 232 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 233 <&mcu_r5fss0_core1_memory_region>; 234}; 235 236&main_r5fss0_core0 { 237 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; 238 memory-region = <&main_r5fss0_core0_dma_memory_region>, 239 <&main_r5fss0_core0_memory_region>; 240}; 241 242&main_r5fss0_core1 { 243 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; 244 memory-region = <&main_r5fss0_core1_dma_memory_region>, 245 <&main_r5fss0_core1_memory_region>; 246}; 247 248&main_i2c0 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&main_i2c0_pins_default>; 251 clock-frequency = <400000>; 252 253 exp_som: gpio@21 { 254 compatible = "ti,tca6408"; 255 reg = <0x21>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 259 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 260 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", 261 "GPIO_LIN_EN", "CAN_STB"; 262 }; 263}; 264 265&wkup_i2c0 { 266 status = "okay"; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&wkup_i2c0_pins_default>; 269 clock-frequency = <400000>; 270 271 eeprom@50 { 272 compatible = "atmel,24c256"; 273 reg = <0x50>; 274 }; 275 276 tps659414: pmic@48 { 277 compatible = "ti,tps6594-q1"; 278 reg = <0x48>; 279 system-power-controller; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pmic_irq_pins_default>; 282 interrupt-parent = <&wkup_gpio0>; 283 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 284 gpio-controller; 285 #gpio-cells = <2>; 286 ti,primary-pmic; 287 buck1-supply = <&vsys_3v3>; 288 buck2-supply = <&vsys_3v3>; 289 buck3-supply = <&vsys_3v3>; 290 buck4-supply = <&vsys_3v3>; 291 buck5-supply = <&vsys_3v3>; 292 ldo1-supply = <&vsys_3v3>; 293 ldo2-supply = <&vsys_3v3>; 294 ldo3-supply = <&vsys_3v3>; 295 ldo4-supply = <&vsys_3v3>; 296 297 regulators { 298 bucka1: buck1 { 299 regulator-name = "vda_mcu_1v8"; 300 regulator-min-microvolt = <1800000>; 301 regulator-max-microvolt = <1800000>; 302 regulator-boot-on; 303 regulator-always-on; 304 }; 305 306 bucka2: buck2 { 307 regulator-name = "vdd_mcuio_1v8"; 308 regulator-min-microvolt = <1800000>; 309 regulator-max-microvolt = <1800000>; 310 regulator-boot-on; 311 regulator-always-on; 312 }; 313 314 bucka3: buck3 { 315 regulator-name = "vdd_mcu_0v85"; 316 regulator-min-microvolt = <850000>; 317 regulator-max-microvolt = <850000>; 318 regulator-boot-on; 319 regulator-always-on; 320 }; 321 322 bucka4: buck4 { 323 regulator-name = "vdd_ddr_1v1"; 324 regulator-min-microvolt = <1100000>; 325 regulator-max-microvolt = <1100000>; 326 regulator-boot-on; 327 regulator-always-on; 328 }; 329 330 bucka5: buck5 { 331 regulator-name = "vdd_phyio_1v8"; 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-boot-on; 335 regulator-always-on; 336 }; 337 338 ldoa1: ldo1 { 339 regulator-name = "vdd1_lpddr4_1v8"; 340 regulator-min-microvolt = <1800000>; 341 regulator-max-microvolt = <1800000>; 342 regulator-boot-on; 343 regulator-always-on; 344 }; 345 346 ldoa2: ldo2 { 347 regulator-name = "vda_dll_0v8"; 348 regulator-min-microvolt = <800000>; 349 regulator-max-microvolt = <800000>; 350 regulator-boot-on; 351 regulator-always-on; 352 }; 353 354 ldoa3: ldo3 { 355 regulator-name = "vdd_wk_0v8"; 356 regulator-min-microvolt = <800000>; 357 regulator-max-microvolt = <800000>; 358 regulator-boot-on; 359 regulator-always-on; 360 }; 361 362 ldoa4: ldo4 { 363 regulator-name = "vda_pll_1v8"; 364 regulator-min-microvolt = <1800000>; 365 regulator-max-microvolt = <1800000>; 366 regulator-boot-on; 367 regulator-always-on; 368 }; 369 }; 370 }; 371 372 lp876441: pmic@4c { 373 compatible = "ti,lp8764-q1"; 374 reg = <0x4c>; 375 system-power-controller; 376 interrupt-parent = <&wkup_gpio0>; 377 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 buck1-supply = <&vsys_3v3>; 381 buck2-supply = <&vsys_3v3>; 382 buck3-supply = <&vsys_3v3>; 383 buck4-supply = <&vsys_3v3>; 384 385 regulators: regulators { 386 buckb1: buck1 { 387 regulator-name = "vdd_cpu_avs"; 388 regulator-min-microvolt = <600000>; 389 regulator-max-microvolt = <900000>; 390 regulator-always-on; 391 regulator-boot-on; 392 bootph-pre-ram; 393 }; 394 395 buckb2: buck2 { 396 regulator-name = "vdd_ram_0v85"; 397 regulator-min-microvolt = <850000>; 398 regulator-max-microvolt = <850000>; 399 regulator-boot-on; 400 regulator-always-on; 401 }; 402 403 buckb3: buck3 { 404 regulator-name = "vdd_core_0v85"; 405 regulator-min-microvolt = <850000>; 406 regulator-max-microvolt = <850000>; 407 regulator-boot-on; 408 regulator-always-on; 409 }; 410 411 buckb4: buck4 { 412 regulator-name = "vdd_io_1v8"; 413 regulator-min-microvolt = <1800000>; 414 regulator-max-microvolt = <1800000>; 415 regulator-boot-on; 416 regulator-always-on; 417 }; 418 }; 419 }; 420}; 421 422&ospi0 { 423 status = "okay"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 426 427 flash@0 { 428 compatible = "jedec,spi-nor"; 429 reg = <0x0>; 430 spi-tx-bus-width = <8>; 431 spi-rx-bus-width = <8>; 432 spi-max-frequency = <25000000>; 433 cdns,tshsl-ns = <60>; 434 cdns,tsd2d-ns = <60>; 435 cdns,tchsh-ns = <60>; 436 cdns,tslch-ns = <60>; 437 cdns,read-delay = <4>; 438 439 partitions { 440 compatible = "fixed-partitions"; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 444 partition@0 { 445 label = "ospi.tiboot3"; 446 reg = <0x0 0x100000>; 447 }; 448 449 partition@100000 { 450 label = "ospi.tispl"; 451 reg = <0x100000 0x200000>; 452 }; 453 454 partition@300000 { 455 label = "ospi.u-boot"; 456 reg = <0x300000 0x400000>; 457 }; 458 459 partition@700000 { 460 label = "ospi.env"; 461 reg = <0x700000 0x40000>; 462 }; 463 464 partition@740000 { 465 label = "ospi.env.backup"; 466 reg = <0x740000 0x40000>; 467 }; 468 469 partition@800000 { 470 label = "ospi.rootfs"; 471 reg = <0x800000 0x37c0000>; 472 }; 473 474 partition@3fc0000 { 475 label = "ospi.phypattern"; 476 reg = <0x3fc0000 0x40000>; 477 }; 478 }; 479 }; 480}; 481