1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 58 59 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 60 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 61 62 gic_its: msi-controller@1820000 { 63 compatible = "arm,gic-v3-its"; 64 reg = <0x00 0x01820000 0x00 0x10000>; 65 socionext,synquacer-pre-its = <0x1000000 0x400000>; 66 msi-controller; 67 #msi-cells = <1>; 68 }; 69 }; 70 71 main_gpio_intr: interrupt-controller@a00000 { 72 compatible = "ti,sci-intr"; 73 reg = <0x00 0x00a00000 0x00 0x800>; 74 ti,intr-trigger-type = <1>; 75 interrupt-controller; 76 interrupt-parent = <&gic500>; 77 #interrupt-cells = <1>; 78 ti,sci = <&dmsc>; 79 ti,sci-dev-id = <131>; 80 ti,interrupt-ranges = <8 392 56>; 81 }; 82 83 main_navss: bus@30000000 { 84 compatible = "simple-mfd"; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 88 ti,sci-dev-id = <199>; 89 dma-coherent; 90 dma-ranges; 91 92 main_navss_intr: interrupt-controller@310e0000 { 93 compatible = "ti,sci-intr"; 94 reg = <0x00 0x310e0000 0x00 0x4000>; 95 ti,intr-trigger-type = <4>; 96 interrupt-controller; 97 interrupt-parent = <&gic500>; 98 #interrupt-cells = <1>; 99 ti,sci = <&dmsc>; 100 ti,sci-dev-id = <213>; 101 ti,interrupt-ranges = <0 64 64>, 102 <64 448 64>, 103 <128 672 64>; 104 }; 105 106 main_udmass_inta: msi-controller@33d00000 { 107 compatible = "ti,sci-inta"; 108 reg = <0x00 0x33d00000 0x00 0x100000>; 109 interrupt-controller; 110 #interrupt-cells = <0>; 111 interrupt-parent = <&main_navss_intr>; 112 msi-controller; 113 ti,sci = <&dmsc>; 114 ti,sci-dev-id = <209>; 115 ti,interrupt-ranges = <0 0 256>; 116 }; 117 118 secure_proxy_main: mailbox@32c00000 { 119 compatible = "ti,am654-secure-proxy"; 120 #mbox-cells = <1>; 121 reg-names = "target_data", "rt", "scfg"; 122 reg = <0x00 0x32c00000 0x00 0x100000>, 123 <0x00 0x32400000 0x00 0x100000>, 124 <0x00 0x32800000 0x00 0x100000>; 125 interrupt-names = "rx_011"; 126 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 127 }; 128 129 hwspinlock: spinlock@30e00000 { 130 compatible = "ti,am654-hwspinlock"; 131 reg = <0x00 0x30e00000 0x00 0x1000>; 132 #hwlock-cells = <1>; 133 }; 134 135 mailbox0_cluster0: mailbox@31f80000 { 136 compatible = "ti,am654-mailbox"; 137 reg = <0x00 0x31f80000 0x00 0x200>; 138 #mbox-cells = <1>; 139 ti,mbox-num-users = <4>; 140 ti,mbox-num-fifos = <16>; 141 interrupt-parent = <&main_navss_intr>; 142 }; 143 144 mailbox0_cluster1: mailbox@31f81000 { 145 compatible = "ti,am654-mailbox"; 146 reg = <0x00 0x31f81000 0x00 0x200>; 147 #mbox-cells = <1>; 148 ti,mbox-num-users = <4>; 149 ti,mbox-num-fifos = <16>; 150 interrupt-parent = <&main_navss_intr>; 151 }; 152 153 mailbox0_cluster2: mailbox@31f82000 { 154 compatible = "ti,am654-mailbox"; 155 reg = <0x00 0x31f82000 0x00 0x200>; 156 #mbox-cells = <1>; 157 ti,mbox-num-users = <4>; 158 ti,mbox-num-fifos = <16>; 159 interrupt-parent = <&main_navss_intr>; 160 }; 161 162 mailbox0_cluster3: mailbox@31f83000 { 163 compatible = "ti,am654-mailbox"; 164 reg = <0x00 0x31f83000 0x00 0x200>; 165 #mbox-cells = <1>; 166 ti,mbox-num-users = <4>; 167 ti,mbox-num-fifos = <16>; 168 interrupt-parent = <&main_navss_intr>; 169 }; 170 171 mailbox0_cluster4: mailbox@31f84000 { 172 compatible = "ti,am654-mailbox"; 173 reg = <0x00 0x31f84000 0x00 0x200>; 174 #mbox-cells = <1>; 175 ti,mbox-num-users = <4>; 176 ti,mbox-num-fifos = <16>; 177 interrupt-parent = <&main_navss_intr>; 178 }; 179 180 mailbox0_cluster5: mailbox@31f85000 { 181 compatible = "ti,am654-mailbox"; 182 reg = <0x00 0x31f85000 0x00 0x200>; 183 #mbox-cells = <1>; 184 ti,mbox-num-users = <4>; 185 ti,mbox-num-fifos = <16>; 186 interrupt-parent = <&main_navss_intr>; 187 }; 188 189 mailbox0_cluster6: mailbox@31f86000 { 190 compatible = "ti,am654-mailbox"; 191 reg = <0x00 0x31f86000 0x00 0x200>; 192 #mbox-cells = <1>; 193 ti,mbox-num-users = <4>; 194 ti,mbox-num-fifos = <16>; 195 interrupt-parent = <&main_navss_intr>; 196 }; 197 198 mailbox0_cluster7: mailbox@31f87000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f87000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 }; 206 207 mailbox0_cluster8: mailbox@31f88000 { 208 compatible = "ti,am654-mailbox"; 209 reg = <0x00 0x31f88000 0x00 0x200>; 210 #mbox-cells = <1>; 211 ti,mbox-num-users = <4>; 212 ti,mbox-num-fifos = <16>; 213 interrupt-parent = <&main_navss_intr>; 214 }; 215 216 mailbox0_cluster9: mailbox@31f89000 { 217 compatible = "ti,am654-mailbox"; 218 reg = <0x00 0x31f89000 0x00 0x200>; 219 #mbox-cells = <1>; 220 ti,mbox-num-users = <4>; 221 ti,mbox-num-fifos = <16>; 222 interrupt-parent = <&main_navss_intr>; 223 }; 224 225 mailbox0_cluster10: mailbox@31f8a000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f8a000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 }; 233 234 mailbox0_cluster11: mailbox@31f8b000 { 235 compatible = "ti,am654-mailbox"; 236 reg = <0x00 0x31f8b000 0x00 0x200>; 237 #mbox-cells = <1>; 238 ti,mbox-num-users = <4>; 239 ti,mbox-num-fifos = <16>; 240 interrupt-parent = <&main_navss_intr>; 241 }; 242 243 main_ringacc: ringacc@3c000000 { 244 compatible = "ti,am654-navss-ringacc"; 245 reg = <0x00 0x3c000000 0x00 0x400000>, 246 <0x00 0x38000000 0x00 0x400000>, 247 <0x00 0x31120000 0x00 0x100>, 248 <0x00 0x33000000 0x00 0x40000>; 249 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 250 ti,num-rings = <1024>; 251 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 252 ti,sci = <&dmsc>; 253 ti,sci-dev-id = <211>; 254 msi-parent = <&main_udmass_inta>; 255 }; 256 257 main_udmap: dma-controller@31150000 { 258 compatible = "ti,j721e-navss-main-udmap"; 259 reg = <0x00 0x31150000 0x00 0x100>, 260 <0x00 0x34000000 0x00 0x100000>, 261 <0x00 0x35000000 0x00 0x100000>; 262 reg-names = "gcfg", "rchanrt", "tchanrt"; 263 msi-parent = <&main_udmass_inta>; 264 #dma-cells = <1>; 265 266 ti,sci = <&dmsc>; 267 ti,sci-dev-id = <212>; 268 ti,ringacc = <&main_ringacc>; 269 270 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 271 <0x0f>, /* TX_HCHAN */ 272 <0x10>; /* TX_UHCHAN */ 273 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 274 <0x0b>, /* RX_HCHAN */ 275 <0x0c>; /* RX_UHCHAN */ 276 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 277 }; 278 279 cpts@310d0000 { 280 compatible = "ti,j721e-cpts"; 281 reg = <0x00 0x310d0000 0x00 0x400>; 282 reg-names = "cpts"; 283 clocks = <&k3_clks 201 1>; 284 clock-names = "cpts"; 285 interrupts-extended = <&main_navss_intr 391>; 286 interrupt-names = "cpts"; 287 ti,cpts-periodic-outputs = <6>; 288 ti,cpts-ext-ts-inputs = <8>; 289 }; 290 }; 291 292 main_pmx0: pinctrl@11c000 { 293 compatible = "pinctrl-single"; 294 /* Proxy 0 addressing */ 295 reg = <0x00 0x11c000 0x00 0x2b4>; 296 #pinctrl-cells = <1>; 297 pinctrl-single,register-width = <32>; 298 pinctrl-single,function-mask = <0xffffffff>; 299 }; 300 301 main_uart0: serial@2800000 { 302 compatible = "ti,j721e-uart", "ti,am654-uart"; 303 reg = <0x00 0x02800000 0x00 0x100>; 304 reg-shift = <2>; 305 reg-io-width = <4>; 306 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 307 clock-frequency = <48000000>; 308 current-speed = <115200>; 309 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 310 clocks = <&k3_clks 146 2>; 311 clock-names = "fclk"; 312 }; 313 314 main_uart1: serial@2810000 { 315 compatible = "ti,j721e-uart", "ti,am654-uart"; 316 reg = <0x00 0x02810000 0x00 0x100>; 317 reg-shift = <2>; 318 reg-io-width = <4>; 319 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 320 clock-frequency = <48000000>; 321 current-speed = <115200>; 322 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 323 clocks = <&k3_clks 278 2>; 324 clock-names = "fclk"; 325 }; 326 327 main_uart2: serial@2820000 { 328 compatible = "ti,j721e-uart", "ti,am654-uart"; 329 reg = <0x00 0x02820000 0x00 0x100>; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 333 clock-frequency = <48000000>; 334 current-speed = <115200>; 335 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 279 2>; 337 clock-names = "fclk"; 338 }; 339 340 main_uart3: serial@2830000 { 341 compatible = "ti,j721e-uart", "ti,am654-uart"; 342 reg = <0x00 0x02830000 0x00 0x100>; 343 reg-shift = <2>; 344 reg-io-width = <4>; 345 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 346 clock-frequency = <48000000>; 347 current-speed = <115200>; 348 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 349 clocks = <&k3_clks 280 2>; 350 clock-names = "fclk"; 351 }; 352 353 main_uart4: serial@2840000 { 354 compatible = "ti,j721e-uart", "ti,am654-uart"; 355 reg = <0x00 0x02840000 0x00 0x100>; 356 reg-shift = <2>; 357 reg-io-width = <4>; 358 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 359 clock-frequency = <48000000>; 360 current-speed = <115200>; 361 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 362 clocks = <&k3_clks 281 2>; 363 clock-names = "fclk"; 364 }; 365 366 main_uart5: serial@2850000 { 367 compatible = "ti,j721e-uart", "ti,am654-uart"; 368 reg = <0x00 0x02850000 0x00 0x100>; 369 reg-shift = <2>; 370 reg-io-width = <4>; 371 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 372 clock-frequency = <48000000>; 373 current-speed = <115200>; 374 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 375 clocks = <&k3_clks 282 2>; 376 clock-names = "fclk"; 377 }; 378 379 main_uart6: serial@2860000 { 380 compatible = "ti,j721e-uart", "ti,am654-uart"; 381 reg = <0x00 0x02860000 0x00 0x100>; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 385 clock-frequency = <48000000>; 386 current-speed = <115200>; 387 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 388 clocks = <&k3_clks 283 2>; 389 clock-names = "fclk"; 390 }; 391 392 main_uart7: serial@2870000 { 393 compatible = "ti,j721e-uart", "ti,am654-uart"; 394 reg = <0x00 0x02870000 0x00 0x100>; 395 reg-shift = <2>; 396 reg-io-width = <4>; 397 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 398 clock-frequency = <48000000>; 399 current-speed = <115200>; 400 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 284 2>; 402 clock-names = "fclk"; 403 }; 404 405 main_uart8: serial@2880000 { 406 compatible = "ti,j721e-uart", "ti,am654-uart"; 407 reg = <0x00 0x02880000 0x00 0x100>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 411 clock-frequency = <48000000>; 412 current-speed = <115200>; 413 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 414 clocks = <&k3_clks 285 2>; 415 clock-names = "fclk"; 416 }; 417 418 main_uart9: serial@2890000 { 419 compatible = "ti,j721e-uart", "ti,am654-uart"; 420 reg = <0x00 0x02890000 0x00 0x100>; 421 reg-shift = <2>; 422 reg-io-width = <4>; 423 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 424 clock-frequency = <48000000>; 425 current-speed = <115200>; 426 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 286 2>; 428 clock-names = "fclk"; 429 }; 430 431 main_i2c0: i2c@2000000 { 432 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 433 reg = <0x00 0x2000000 0x00 0x100>; 434 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 clock-names = "fck"; 438 clocks = <&k3_clks 187 1>; 439 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 440 }; 441 442 main_i2c1: i2c@2010000 { 443 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 444 reg = <0x00 0x2010000 0x00 0x100>; 445 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 clock-names = "fck"; 449 clocks = <&k3_clks 188 1>; 450 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 451 }; 452 453 main_i2c2: i2c@2020000 { 454 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 455 reg = <0x00 0x2020000 0x00 0x100>; 456 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clock-names = "fck"; 460 clocks = <&k3_clks 189 1>; 461 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 462 }; 463 464 main_i2c3: i2c@2030000 { 465 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 466 reg = <0x00 0x2030000 0x00 0x100>; 467 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clock-names = "fck"; 471 clocks = <&k3_clks 190 1>; 472 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 473 }; 474 475 main_i2c4: i2c@2040000 { 476 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 477 reg = <0x00 0x2040000 0x00 0x100>; 478 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clock-names = "fck"; 482 clocks = <&k3_clks 191 1>; 483 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 484 }; 485 486 main_i2c5: i2c@2050000 { 487 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 488 reg = <0x00 0x2050000 0x00 0x100>; 489 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clock-names = "fck"; 493 clocks = <&k3_clks 192 1>; 494 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 495 }; 496 497 main_i2c6: i2c@2060000 { 498 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 499 reg = <0x00 0x2060000 0x00 0x100>; 500 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 clock-names = "fck"; 504 clocks = <&k3_clks 193 1>; 505 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 506 }; 507 508 main_sdhci0: mmc@4f80000 { 509 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 510 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 511 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 512 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 513 clock-names = "clk_ahb", "clk_xin"; 514 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 515 ti,otap-del-sel-legacy = <0x0>; 516 ti,otap-del-sel-mmc-hs = <0x0>; 517 ti,otap-del-sel-ddr52 = <0x6>; 518 ti,otap-del-sel-hs200 = <0x8>; 519 ti,otap-del-sel-hs400 = <0x5>; 520 ti,itap-del-sel-legacy = <0x10>; 521 ti,itap-del-sel-mmc-hs = <0xa>; 522 ti,strobe-sel = <0x77>; 523 ti,clkbuf-sel = <0x7>; 524 ti,trm-icp = <0x8>; 525 bus-width = <8>; 526 mmc-ddr-1_8v; 527 mmc-hs200-1_8v; 528 mmc-hs400-1_8v; 529 dma-coherent; 530 }; 531 532 main_sdhci1: mmc@4fb0000 { 533 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 534 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 535 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 536 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 537 clock-names = "clk_ahb", "clk_xin"; 538 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 539 ti,otap-del-sel-legacy = <0x0>; 540 ti,otap-del-sel-sd-hs = <0x0>; 541 ti,otap-del-sel-sdr12 = <0xf>; 542 ti,otap-del-sel-sdr25 = <0xf>; 543 ti,otap-del-sel-sdr50 = <0xc>; 544 ti,otap-del-sel-sdr104 = <0x5>; 545 ti,otap-del-sel-ddr50 = <0xc>; 546 ti,itap-del-sel-legacy = <0x0>; 547 ti,itap-del-sel-sd-hs = <0x0>; 548 ti,itap-del-sel-sdr12 = <0x0>; 549 ti,itap-del-sel-sdr25 = <0x0>; 550 ti,clkbuf-sel = <0x7>; 551 ti,trm-icp = <0x8>; 552 dma-coherent; 553 }; 554 555 serdes_wiz0: wiz@5060000 { 556 compatible = "ti,j721e-wiz-10g"; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 560 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 561 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 562 num-lanes = <4>; 563 #reset-cells = <1>; 564 ranges = <0x5060000 0x0 0x5060000 0x10000>; 565 566 assigned-clocks = <&k3_clks 292 85>; 567 assigned-clock-parents = <&k3_clks 292 89>; 568 569 wiz0_pll0_refclk: pll0-refclk { 570 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 571 clock-output-names = "wiz0_pll0_refclk"; 572 #clock-cells = <0>; 573 assigned-clocks = <&wiz0_pll0_refclk>; 574 assigned-clock-parents = <&k3_clks 292 85>; 575 }; 576 577 wiz0_pll1_refclk: pll1-refclk { 578 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 579 clock-output-names = "wiz0_pll1_refclk"; 580 #clock-cells = <0>; 581 assigned-clocks = <&wiz0_pll1_refclk>; 582 assigned-clock-parents = <&k3_clks 292 85>; 583 }; 584 585 wiz0_refclk_dig: refclk-dig { 586 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 587 clock-output-names = "wiz0_refclk_dig"; 588 #clock-cells = <0>; 589 assigned-clocks = <&wiz0_refclk_dig>; 590 assigned-clock-parents = <&k3_clks 292 85>; 591 }; 592 593 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 594 clocks = <&wiz0_refclk_dig>; 595 #clock-cells = <0>; 596 }; 597 598 serdes0: serdes@5060000 { 599 compatible = "ti,j721e-serdes-10g"; 600 reg = <0x05060000 0x00010000>; 601 reg-names = "torrent_phy"; 602 resets = <&serdes_wiz0 0>; 603 reset-names = "torrent_reset"; 604 clocks = <&wiz0_pll0_refclk>; 605 clock-names = "refclk"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 }; 609 }; 610 611 pcie1_rc: pcie@2910000 { 612 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 613 reg = <0x00 0x02910000 0x00 0x1000>, 614 <0x00 0x02917000 0x00 0x400>, 615 <0x00 0x0d800000 0x00 0x00800000>, 616 <0x00 0x18000000 0x00 0x00001000>; 617 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 618 interrupt-names = "link_state"; 619 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 620 device_type = "pci"; 621 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 622 max-link-speed = <3>; 623 num-lanes = <4>; 624 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 625 clocks = <&k3_clks 240 6>; 626 clock-names = "fck"; 627 #address-cells = <3>; 628 #size-cells = <2>; 629 bus-range = <0x0 0xf>; 630 cdns,no-bar-match-nbits = <64>; 631 vendor-id = /bits/ 16 <0x104c>; 632 device-id = /bits/ 16 <0xb00f>; 633 msi-map = <0x0 &gic_its 0x0 0x10000>; 634 dma-coherent; 635 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 636 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 637 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 638 }; 639 640 pcie1_ep: pcie-ep@2910000 { 641 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 642 reg = <0x00 0x02910000 0x00 0x1000>, 643 <0x00 0x02917000 0x00 0x400>, 644 <0x00 0x0d800000 0x00 0x00800000>, 645 <0x00 0x18000000 0x00 0x08000000>; 646 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 647 interrupt-names = "link_state"; 648 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 649 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 650 max-link-speed = <3>; 651 num-lanes = <4>; 652 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 653 clocks = <&k3_clks 240 6>; 654 clock-names = "fck"; 655 max-functions = /bits/ 8 <6>; 656 dma-coherent; 657 }; 658 659 usbss0: cdns-usb@4104000 { 660 compatible = "ti,j721e-usb"; 661 reg = <0x00 0x4104000 0x00 0x100>; 662 dma-coherent; 663 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 664 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 665 clock-names = "ref", "lpm"; 666 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 667 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 668 #address-cells = <2>; 669 #size-cells = <2>; 670 ranges; 671 672 usb0: usb@6000000 { 673 compatible = "cdns,usb3"; 674 reg = <0x00 0x6000000 0x00 0x10000>, 675 <0x00 0x6010000 0x00 0x10000>, 676 <0x00 0x6020000 0x00 0x10000>; 677 reg-names = "otg", "xhci", "dev"; 678 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 679 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 680 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 681 interrupt-names = "host", 682 "peripheral", 683 "otg"; 684 maximum-speed = "super-speed"; 685 dr_mode = "otg"; 686 }; 687 }; 688 689 main_gpio0: gpio@600000 { 690 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 691 reg = <0x00 0x00600000 0x00 0x100>; 692 gpio-controller; 693 #gpio-cells = <2>; 694 interrupt-parent = <&main_gpio_intr>; 695 interrupts = <145>, <146>, <147>, <148>, 696 <149>; 697 interrupt-controller; 698 #interrupt-cells = <2>; 699 #address-cells = <0>; 700 ti,ngpio = <69>; 701 ti,davinci-gpio-unbanked = <0>; 702 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 703 clocks = <&k3_clks 105 0>; 704 clock-names = "gpio"; 705 }; 706 707 main_gpio2: gpio@610000 { 708 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 709 reg = <0x00 0x00610000 0x00 0x100>; 710 gpio-controller; 711 #gpio-cells = <2>; 712 interrupt-parent = <&main_gpio_intr>; 713 interrupts = <154>, <155>, <156>, <157>, 714 <158>; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 #address-cells = <0>; 718 ti,ngpio = <69>; 719 ti,davinci-gpio-unbanked = <0>; 720 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 721 clocks = <&k3_clks 107 0>; 722 clock-names = "gpio"; 723 }; 724 725 main_gpio4: gpio@620000 { 726 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 727 reg = <0x00 0x00620000 0x00 0x100>; 728 gpio-controller; 729 #gpio-cells = <2>; 730 interrupt-parent = <&main_gpio_intr>; 731 interrupts = <163>, <164>, <165>, <166>, 732 <167>; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 #address-cells = <0>; 736 ti,ngpio = <69>; 737 ti,davinci-gpio-unbanked = <0>; 738 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 739 clocks = <&k3_clks 109 0>; 740 clock-names = "gpio"; 741 }; 742 743 main_gpio6: gpio@630000 { 744 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 745 reg = <0x00 0x00630000 0x00 0x100>; 746 gpio-controller; 747 #gpio-cells = <2>; 748 interrupt-parent = <&main_gpio_intr>; 749 interrupts = <172>, <173>, <174>, <175>, 750 <176>; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 #address-cells = <0>; 754 ti,ngpio = <69>; 755 ti,davinci-gpio-unbanked = <0>; 756 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 757 clocks = <&k3_clks 111 0>; 758 clock-names = "gpio"; 759 }; 760 761 main_r5fss0: r5fss@5c00000 { 762 compatible = "ti,j7200-r5fss"; 763 ti,cluster-mode = <1>; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 767 <0x5d00000 0x00 0x5d00000 0x20000>; 768 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 769 770 main_r5fss0_core0: r5f@5c00000 { 771 compatible = "ti,j7200-r5f"; 772 reg = <0x5c00000 0x00010000>, 773 <0x5c10000 0x00010000>; 774 reg-names = "atcm", "btcm"; 775 ti,sci = <&dmsc>; 776 ti,sci-dev-id = <245>; 777 ti,sci-proc-ids = <0x06 0xff>; 778 resets = <&k3_reset 245 1>; 779 firmware-name = "j7200-main-r5f0_0-fw"; 780 ti,atcm-enable = <1>; 781 ti,btcm-enable = <1>; 782 ti,loczrama = <1>; 783 }; 784 785 main_r5fss0_core1: r5f@5d00000 { 786 compatible = "ti,j7200-r5f"; 787 reg = <0x5d00000 0x00008000>, 788 <0x5d10000 0x00008000>; 789 reg-names = "atcm", "btcm"; 790 ti,sci = <&dmsc>; 791 ti,sci-dev-id = <246>; 792 ti,sci-proc-ids = <0x07 0xff>; 793 resets = <&k3_reset 246 1>; 794 firmware-name = "j7200-main-r5f0_1-fw"; 795 ti,atcm-enable = <1>; 796 ti,btcm-enable = <1>; 797 ti,loczrama = <1>; 798 }; 799 }; 800}; 801