1// SPDX-License-Identifier: GPL-2.0 2/** 3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with 4 * J7200 board. 5 * 6 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9/dts-v1/; 10/plugin/; 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mux/ti-serdes.h> 14 15#include "k3-pinctrl.h" 16 17&{/} { 18 aliases { 19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 22 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 23 }; 24}; 25 26&cpsw0 { 27 status = "okay"; 28}; 29 30&cpsw0_port1 { 31 status = "okay"; 32 phy-handle = <&cpsw5g_phy0>; 33 phy-mode = "qsgmii"; 34 mac-address = [00 00 00 00 00 00]; 35 phys = <&cpsw0_phy_gmii_sel 1>; 36}; 37 38&cpsw0_port2 { 39 status = "okay"; 40 phy-handle = <&cpsw5g_phy1>; 41 phy-mode = "qsgmii"; 42 mac-address = [00 00 00 00 00 00]; 43 phys = <&cpsw0_phy_gmii_sel 2>; 44}; 45 46&cpsw0_port3 { 47 status = "okay"; 48 phy-handle = <&cpsw5g_phy2>; 49 phy-mode = "qsgmii"; 50 mac-address = [00 00 00 00 00 00]; 51 phys = <&cpsw0_phy_gmii_sel 3>; 52}; 53 54&cpsw0_port4 { 55 status = "okay"; 56 phy-handle = <&cpsw5g_phy3>; 57 phy-mode = "qsgmii"; 58 mac-address = [00 00 00 00 00 00]; 59 phys = <&cpsw0_phy_gmii_sel 4>; 60}; 61 62&cpsw5g_mdio { 63 status = "okay"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&mdio0_pins_default>; 66 reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; 67 reset-post-delay-us = <120000>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 cpsw5g_phy0: ethernet-phy@16 { 72 reg = <16>; 73 }; 74 cpsw5g_phy1: ethernet-phy@17 { 75 reg = <17>; 76 }; 77 cpsw5g_phy2: ethernet-phy@18 { 78 reg = <18>; 79 }; 80 cpsw5g_phy3: ethernet-phy@19 { 81 reg = <19>; 82 }; 83}; 84 85&exp2 { 86 qsgmii-line-hog { 87 gpio-hog; 88 gpios = <16 GPIO_ACTIVE_HIGH>; 89 output-low; 90 line-name = "qsgmii-pwrdn-line"; 91 }; 92}; 93 94&main_pmx0 { 95 mdio0_pins_default: mdio0-pins-default { 96 pinctrl-single,pins = < 97 J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ 98 J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ 99 >; 100 }; 101}; 102